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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 12 occurrences of 8 keywords
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Results
Found 7 publication records. Showing 7 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 36 | Felipe S. Marques 0001, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis |
DAG based library-free technology mapping.  |
ACM Great Lakes Symposium on VLSI  |
2007 |
DBLP DOI BibTeX RDF |
library free synthesis, logic synthesis, technology mapping, switching theory, virtual libraries |
| 18 | Vinícius P. Correia, André Inácio Reis |
Advanced technology mapping for standard-cell generators. |
SBCCI |
2004 |
DBLP DOI BibTeX RDF |
cell library, library-free, logic synthesis, technology mapping, complex gates |
| 12 | Maximilian Neuner, Inga Abel, Helmut Graeb |
Library-free Structure Recognition for Analog Circuits. |
DATE |
2021 |
DBLP DOI BibTeX RDF |
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| 12 | Jiajie Zeng, Xiaohai Dai, Jiang Xiao, Wenhui Yang, Weifeng Hao, Hai Jin 0001 |
BookChain: Library-Free Book Sharing Based on Blockchain Technology. |
MSN |
2019 |
DBLP DOI BibTeX RDF |
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| 12 | Hisham El-Masry, Dhamin Al-Khalili |
Cell stack length using an enhanced logical effort model for a library-free paradigm. |
ICECS |
2011 |
DBLP DOI BibTeX RDF |
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| 12 | A. Reis, R. Reis, M. Robert |
Topological Parameters for Library Free Technology Mapping. |
SBCCI |
1998 |
DBLP DOI BibTeX RDF |
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| 10 | Leomar S. da Rosa Jr., André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Felipe Ribeiro Schneider |
A comparative study of CMOS gates with minimum transistor stacks. |
SBCCI |
2007 |
DBLP DOI BibTeX RDF |
PTL, unateness, BDDs, technology mapping, switch theory, logical effort, CMOS gates |
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