Search results for "modulo"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
103	Daniel M. Lavery, Wen-mei W. Hwu	Modulo Scheduling of Loops in Control-intensive Non-numeric Programs.	MICRO	1996	DBLP DOI BibTeX RDF	control-intensive, modulo variable expansion, instruction-level parallelism, software pipelining, speculation, modulo scheduling
89	Clément Houtmann	Axiom Directed Focusing.	TYPES	2008	DBLP DOI BibTeX RDF	superdeduction, Proof theory, focusing, deduction modulo
85	Yosi Ben-Asher, Danny Meisler	Towards a Source Level Compiler: Source Level Modulo Scheduling.	Program Analysis and Compilation	2006	DBLP DOI BibTeX RDF
85	Yosi Ben-Asher, Danny Meisler	Towards a Source Level Compiler: Source Level Modulo Scheduling.	ICPP Workshops	2006	DBLP DOI BibTeX RDF
81	Gilles Dowek, Thérèse Hardin, Claude Kirchner	Theorem Proving Modulo.	J. Autom. Reason.	2003	DBLP DOI BibTeX RDF	sequent calculus modulo, resolution, rewriting, automated theorem proving, higher-order logic, cut elimination, narrowing, Skolemization, deduction modulo
72	Eric Stotzer, Ernst L. Leiss	Modulo scheduling without overlapped lifetimes.	LCTES	2009	DBLP DOI BibTeX RDF	instruction level parallelism, register allocation, software pipelining, modulo scheduling
72	Guillaume Burel, Claude Kirchner	Cut Elimination in Deduction Modulo by Abstract Completion.	LFCS	2007	DBLP DOI BibTeX RDF	Knuth-Bendix completion, automated deduction and interactive theorem proving, proof ordering, abstract canonical system, cut elimination, deduction modulo
71	Edward Chu Yeow Peh, Ying-Chang Liang	Power and modulo loss tradeoff with expanded soft demapper for LDPC coded GMD-THP MIMO systems.	IEEE Trans. Wirel. Commun.	2009	DBLP DOI BibTeX RDF
68	Jean-Luc Beuchat	Some Modular Adders and Multipliers for Field Programmable Gate Arrays.	IPDPS	2003	DBLP DOI BibTeX RDF	modulo m addition, modulo m multiplication, FPGA, Computer arithmetic
63	Shibu Menon, Chip-Hong Chang	A Reconfigurable Multi-Modulus Modulo Multiplier.	APCCAS	2006	DBLP DOI BibTeX RDF
58	Tsuneo Nakanishi, Kazuki Joe, Constantine D. Polychronopoulos, Akira Fukuda	The Modulo Interval: A Simple and Practical Representation for Program Analysis.	IEEE PACT	1999	DBLP DOI BibTeX RDF	modulo, program analysis, dependence analysis, arithmetic, interval
56	Richard Bonichon	TaMeD: A Tableau Method for Deduction Modulo.	IJCAR	2004	DBLP DOI BibTeX RDF
56	Josep Llosa, Stefan M. Freudenberger	Reduced code size modulo scheduling in the absence of hardware support.	MICRO	2002	DBLP DOI BibTeX RDF
52	Klaus Huber	The MacWilliams theorem for two-dimensional modulo metrics.	Appl. Algebra Eng. Commun. Comput.	1996	DBLP DOI BibTeX RDF	Mannheim metric, Two-dimensional Hexagonal Modulo Metric, Two-dimensional squared Euclidean Modulo Metric, MacWilliams theorem, Weight enumerator, Block codes
50	Riyaz A. Patel, Mohammed Benaissa, Said Boussakta	Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Modulo 2n-1 adders, One's complement adders, computer arithmetic, VLSI design, parallel-prefix adders
50	Hyunchul Park 0001, Kevin Fan, Manjunath Kudlur, Scott A. Mahlke	Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures.	CASES	2006	DBLP DOI BibTeX RDF	graph embedding, modulo scheduling, coarse-grained reconfigurable architecture
50	Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos	Modulo 2n±1 Adder Design Using Select-Prefix Blocks.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	modulo 2n± 1 adders, select-prefix adders, computer arithmetic, VLSI architectures
49	Koji Shigemoto, Kensuke Kawakami, Koji Nakano	Accelerating Montgomery Modulo Multiplication for Redundant Radix-64k Number System on the FPGA Using Dual-Port Block RAMs.	EUC (1)	2008	DBLP DOI BibTeX RDF
49	Guillaume Burel	Unbounded Proof-Length Speed-Up in Deduction Modulo.	CSL	2007	DBLP DOI BibTeX RDF	rewriting, arithmetic, higher order logic, proof theory
49	Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung Paek	Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs.	EUC Workshops	2006	DBLP DOI BibTeX RDF
49	ShaoWei Weng, Yao Zhao 0001, Jeng-Shyang Pan 0001	Reversible Watermarking Based on Improved Patchwork Algorithm and Symmetric Modulo Operation.	KES (4)	2005	DBLP DOI BibTeX RDF
49	Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan	A new formulation of fast diminished-one multioperand modulo 2n/+1 adder.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
49	Shaoqiang Bi, Warren J. Gross, Wei Wang 0003, Asim J. Al-Khalili, M. N. S. Swamy	An Area-Reduced Scheme for Modulo 2n-1 Addition/Subtraction.	IWSOC	2005	DBLP DOI BibTeX RDF
49	Matthew C. Merten, Wen-mei W. Hwu	Modulo schedule buffers.	MICRO	2001	DBLP DOI BibTeX RDF
49	Zhongde Wang, Graham A. Jullien, William C. Miller	An efficient tree architecture for modulo 2n+1 multiplication.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
47	Frédéric Blanqui	Rewriting Modulo in Deduction Modulo.	RTA	2003	DBLP DOI BibTeX RDF
45	Hyunok Oh, Nikil D. Dutt, Soonhoi Ha	Shift buffering technique for automatic code synthesis from synchronous dataflow graphs.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	automatic code synthesis, modulo buffering, shift buffering, buffer management, synchronous dataflow
45	Stephen S. Yau, Jackson Chung	On the Design of Modulo Arithmetic Units Based on Cyclic Groups.	IEEE Trans. Computers	1976	DBLP DOI BibTeX RDF	modulo arithmetics, modulo arithmetic units, design, residue number system, cyclic groups, Binary encoding
44	Koji Nakano, Kensuke Kawakami, Koji Shigemoto	RSA encryption and decryption using the redundant number system on the FPGA.	IPDPS	2009	DBLP DOI BibTeX RDF
44	Kazuyuki Amano, Akira Maruoka	Some Properties of MODm Circuits Computing Simple Functions.	CIAC	2003	DBLP DOI BibTeX RDF	modular circuits, composite modulus, lower bounds, Fourier analysis, symmetric functions
43	Clark W. Barrett, Leonardo Mendonça de Moura, Aaron Stump	Design and results of the 2nd annual satisfiability modulo theories competition (SMT-COMP 2006).	Formal Methods Syst. Des.	2007	DBLP DOI BibTeX RDF	Competition, Decision procedures, Automated theorem proving, SMT, Satisfiability modulo theories
43	Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos	Efficient Diminished-1 Modulo 2^n+1 Multipliers.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Modulo 2^n+1 multipliers, Fermat number transform, computer arithmetic, VLSI design, residue number system
43	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	Register Constrained Modulo Scheduling.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	Instruction level parallelism, register allocation, instruction scheduling, modulo scheduling, spill code
43	Josep M. Codina, Josep Llosa, Antonio González 0001	A comparative study of modulo scheduling techniques.	ICS	2002	DBLP DOI BibTeX RDF	instruction level parallel architectures, instruction scheduling, Modulo scheduling, comparative study, quantitative evaluation
43	B. Ramakrishna Rau	Iterative modulo scheduling: an algorithm for software pipelining loops.	MICRO	1994	DBLP DOI BibTeX RDF	software pipelining, instruction scheduling, modulo scheduling, loop scheduling
43	Jean-Pierre Jouannaud, Claude Marché	Completion modulo Associativity, Commutativity and Identity (AC1).	DISCO	1990	DBLP DOI BibTeX RDF	Class rewriting, Constrained rewriting, Completion modulo AC1, Constrained completion, Rewrite orderings, Termination
42	Yuan Chen, Yao Mao, Qunjiao Zhang	On Modulo Linked Graphs.	FAW	2009	DBLP DOI BibTeX RDF
42	Francisco Durán 0001, Salvador Lucas, José Meseguer 0001	Termination Modulo Combinations of Equational Theories.	FroCoS	2009	DBLP DOI BibTeX RDF
42	Hyejung Kim, Yongsang Kim, Hoi-Jun Yoo	A 6.3nJ/op low energy 160-bit modulo-multiplier for elliptic curve cryptography processor.	ISCAS	2008	DBLP DOI BibTeX RDF
42	Sridhar Srinivasan	Modulo transforms - an alternative to lifting.	IEEE Trans. Signal Process.	2006	DBLP DOI BibTeX RDF
42	Kevin Fan, Manjunath Kudlur, Hyunchul Park 0001, Scott A. Mahlke	Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System.	MICRO	2005	DBLP DOI BibTeX RDF
42	Shugang Wei	Number conversions between RNS and mixed-radix number system based on Modulo (2p - 1) signed-digit arithmetic.	SBCCI	2005	DBLP DOI BibTeX RDF
42	Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang	A new design method to modulo 2n-1 squaring.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
42	Jeffrey Sheldon, Walter Lee, Ben Greenwald, Saman P. Amarasinghe	Strength Reduction of Integer Division and Modulo Operations.	LCPC	2001	DBLP DOI BibTeX RDF
42	Debaleena Das, Nur A. Touba, Markus Seuring, Michael Gössel	Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes.	IOLTW	2000	DBLP DOI BibTeX RDF	error detecting codes, Concurrent error detection, self-checking checkers
42	Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham	Minimum register requirements for a modulo schedule.	MICRO	1994	DBLP DOI BibTeX RDF
39	John R. B. Whittlesey	A comparison of the correlational behavior of random number generators for the IBM 360.	Commun. ACM	1968	DBLP DOI BibTeX RDF	32-bit versus 36-bit word size, IBM 360, congruential generators, digital shift-register generators, linear recurrence modulo two, primitive trinomials modulo two, serial correlation, statistical tests for randomness, random numbers, irreducible polynomials, pseudorandom number generators, prime numbers, autocorrelation function
38	Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao	Single-dimension software pipelining for multidimensional loops.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	Software pipelining, loop transformation, modulo scheduling
38	Daniel Kästner, Markus Pister 0002	Generic Software Pipelining at the Assembly Level.	SCOPES	2005	DBLP DOI BibTeX RDF	PROPAN, software pipelining, modulo scheduling, postpass optimization
36	Shaoqiang Bi, Warren J. Gross	The Mixed-Radix Chinese Remainder Theorem and Its Applications to Residue Comparison.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
36	Shugang Wei, Kensuke Shimizu	Error Detection of Arithmetic Circuits Using a Residue Checker with Signed-Digit Number System.	DFT	2001	DBLP DOI BibTeX RDF	residue addition, residue multiplication, signed-digit(SD) number representation, SD adder, error detection, residue number system(RNS)
36	G. B. Fitzpatrick	Synthesis of Binary Ring Counters of Given Periods.	J. ACM	1960	DBLP DOI BibTeX RDF
36	Cristina Borralleras, Salvador Lucas, Rafael Navarro-Marset, Enric Rodríguez-Carbonell, Albert Rubio	Solving Non-linear Polynomial Arithmetic via SAT Modulo Linear Arithmetic.	CADE	2009	DBLP DOI BibTeX RDF	polynomial constraints, SAT modulo theories, program analysis, termination, Constraint solving
36	Miao Wang, Rongcai Zhao, Jianmin Pang, Guoming Cai	Reconstructing Control Flow in Modulo Scheduled Loops.	ACIS-ICIS	2008	DBLP DOI BibTeX RDF	register rotation, modulo scheduling, decompilation, predication execution, conditional branches
36	Kevin Fan, Hyunchul Park 0001, Manjunath Kudlur, Scott A. Mahlke	Modulo scheduling for highly customized datapaths to increase hardware reusability.	CGO	2008	DBLP DOI BibTeX RDF	programmable asic, modulo scheduling, loop accelerator
36	Nikola Vujic, Marc González 0001, Xavier Martorell, Eduard Ayguadé	Automatic Pre-Fetch and Modulo Scheduling Transformations for the Cell BE Architecture.	LCPC	2008	DBLP DOI BibTeX RDF	Cell BE Architecture, Modulo Scheduling, Pre-fetching, Software Cache
36	Hitoshi Ohsaki, Hiroyuki Seki	Languages Modulo Normalization.	FroCoS	2007	DBLP DOI BibTeX RDF	tree automata modulo axioms, equational rewriting, Boolean closedness, hedge automata and XML schema, regularity, decidability
36	François Panneton, Pierre L'Ecuyer, Makoto Matsumoto	Improved long-period generators based on linear recurrences modulo 2.	ACM Trans. Math. Softw.	2006	DBLP DOI BibTeX RDF	GFSR linear recurrence modulo 2, linear feedback shift register, Random number generation, Mersenne twister
36	Robert Nieuwenhuis, Albert Oliveras, Cesare Tinelli	Solving SAT and SAT Modulo Theories: From an abstract Davis--Putnam--Logemann--Loveland procedure to DPLL(T).	J. ACM	2006	DBLP DOI BibTeX RDF	SAT solvers, Satisfiability Modulo Theories
36	Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan, Daniel Marienfeld	Modulo p=3 Checking for a Carry Select Adder.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	concurrent checking, modulo checking, carry select adder
36	Clark W. Barrett, Leonardo Mendonça de Moura, Aaron Stump	Design and Results of the First Satisfiability Modulo Theories Competition (SMT-COMP 2005).	J. Autom. Reason.	2005	DBLP DOI BibTeX RDF	competition, decision procedures, satisfiability modulo theories
36	Kamilla Klonowska, Lars Lundberg, Håkan Lennerstad, Charlie Svahnberg	Using Modulo Rulers for Optimal Recovery Schemes in Distributed Computing.	PRDC	2004	DBLP DOI BibTeX RDF	recovery schemes, modulo sequence, fault tolerance, high performance computing, Golomb rulers
36	Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos	Diminished-One Modulo 2n+1 Adder Design.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Modulo $big. 2^{rm n}+1bigr.$ addition, carry look-ahead addition, diminished-one number representation, VLSI adders, parallel-prefix adders
36	Josep M. Codina, F. Jesús Sánchez, Antonio González 0001	A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors.	IEEE PACT	2001	DBLP DOI BibTeX RDF	register allocation, Modulo scheduling, clustered architectures, spill code, cluster assignment
36	Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos	High-Speed Parallel-Prefix Modulo 2n-1 Adders.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Modulo $2^n-1$ adders, VLSI design, parallel-prefix adders, carry look-ahead adders
34	Xin Li 0009, Marc Moreno Maza, Wei Pan 0001	Computations modulo regular chains.	ISSAC	2009	DBLP DOI BibTeX RDF	fast polynomial arithmetic, regular chain, regular gcd, polynomial systems, triangular decomposition, subresultants
34	Haralabos C. Papadopoulos, Carl-Erik W. Sundberg	Precoded Modulo-Precanceling Systems for Simulcasting Analog FM and Digital Data.	IEEE Trans. Commun.	2008	DBLP DOI BibTeX RDF
34	Camilo Rocha, José Meseguer 0001	Theorem Proving Modulo Based on Boolean Equational Procedures.	RelMiCS	2008	DBLP DOI BibTeX RDF
34	Hyunchul Park 0001, Kevin Fan, Scott A. Mahlke, Taewook Oh, Heeseok Kim, Hong-Seok Kim	Edge-centric modulo scheduling for coarse-grained reconfigurable architectures.	PACT	2008	DBLP DOI BibTeX RDF	operand routing, programmable accelerator, software pipelining, coarse-grained reconfigurable architecture
34	Haridimos T. Vergos, Dimitris Bakalis	On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components.	DSD	2008	DBLP DOI BibTeX RDF
34	Lin Gao 0002, Quan Hoang Nguyen 0001, Lian Li 0002, Jingling Xue, Tin-Fook Ngai	Thread-Sensitive Modulo Scheduling for Multicore Processors.	ICPP	2008	DBLP DOI BibTeX RDF
34	Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung Paek	Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors.	CC	2007	DBLP DOI BibTeX RDF
34	Lisa Allali	Algorithmic Equality in Heyting Arithmetic Modulo.	TYPES	2007	DBLP DOI BibTeX RDF
34	Gyula Györ	Representing the Boolean OR Function by Quadratic Polynomials Modulo 6.	FCT	2007	DBLP DOI BibTeX RDF
34	Chip-Hong Chang, Shibu Menon, Bin Cao, Thambipillai Srikanthan	A configurable dual moduli multi-operand modulo adder.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
34	Jarno K. Tanskanen, Tero Sihvo, Jarkko Niittylahti	Byte and modulo addressable parallel memory architecture for video coding.	IEEE Trans. Circuits Syst. Video Technol.	2004	DBLP DOI BibTeX RDF
34	Siva Anantharaman, Paliath Narendran, Michaël Rusinowitch	Unification Modulo ACUI Plus Distributivity Axioms.	J. Autom. Reason.	2004	DBLP DOI BibTeX RDF	equational unification, counter machines, complexity, decidability, rewriting, set constraints, Post correspondence problem
34	Haridimos T. Vergos, Costas Efstathiou	Diminished-1 Modulo 2n + 1 Squarer Design.	DSD	2004	DBLP DOI BibTeX RDF
34	Alex Fit-Florea, David W. Matula	A Digit-Serial Algorithm for the Discrete Logarithm Modulo 2k.	ASAP	2004	DBLP DOI BibTeX RDF
34	D. V. Ravindra, Y. N. Srikant	Improved Preprocessing Methods for Modulo Scheduling Algorithms.	HiPC	2002	DBLP DOI BibTeX RDF
34	Johann Großschädl	Instruction Set Extension for Long Integer Modulo Arithmetic on RISC-Based Smart Cards.	SBAC-PAD	2002	DBLP DOI BibTeX RDF
34	Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou	High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
34	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	MIRS: Modulo Scheduling with Integrated Register Spilling.	LCPC	2001	DBLP DOI BibTeX RDF	Instruction-Level Parallelism, Register Allocation, Software Pipelining, Spill Code
34	Uma Mahadevan, Kevin Nomura, Roy Dz-Ching Ju, Rick Hank	Applying Data Speculation in Modulo Scheduled Loops.	IEEE PACT	2000	DBLP DOI BibTeX RDF
34	Alexandre E. Eichenberger, Edward S. Davidson	Efficient Formulation for Optimal Modulo Schedulers.	PLDI	1997	DBLP DOI BibTeX RDF
34	Karl C. Posch, Reinhard Posch	Modulo Reduction in Residue Number Systems.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF
34	Philippe Toffin, Marc Girault, Brigitte Vallée	How to Guess l-th Roots Modulo n by Reducing Lattice Bases.	AAECC	1988	DBLP DOI BibTeX RDF
32	Suhyun Kim, Soo-Mook Moon, Jinpyo Park, Kemal Ebcioglu	Unroll-Based Copy Elimination for Enhanced Pipeline Scheduling.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	enhanced pipeline scheduling, unrolling, modulo variable expansion, iterated coalescing, register allocation, Software pipelining, modulo scheduling, renaming, coalescing
31	Grigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis	Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays.	J. Supercomput.	2009	DBLP DOI BibTeX RDF	Coarse-grained reconfigurable arrays, High productivity tools, Modulo scheduling, Architectural exploration, Compiler techniques
31	Mazen Kharbutli, Yan Solihin, Jaejin Lee	Eliminating Conflict Misses Using Prime Number-Based Cache Indexing.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Cache hashing, cache indexing, prime modulo, odd-multiplier displacement, conflict misses
31	Olivier Hermant	Semantic Cut Elimination in the Intuitionistic Sequent Calculus.	TLCA	2005	DBLP DOI BibTeX RDF	intuitionistic sequent calculus, cut admissibility, cut elimination property, semantic, Kripke Structure, deduction modulo
31	Johann Großschädl	A Bit-Serial Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m).	CHES	2001	DBLP DOI BibTeX RDF	iterative modulo multiplication, polynomial basis representation, bit-serial multiplier architecture, smart card crypto-coprocessor, Elliptic curve cryptography, finite field arithmetic
31	Prateek Sarkar, George Nagy, Jiangying Zhou, Daniel P. Lopresti	Spatial Sampling of Printed Patterns.	IEEE Trans. Pattern Anal. Mach. Intell.	1998	DBLP DOI BibTeX RDF	random phase sampling, document defect models, scanner models, modulo-grid diagram, locales, optical character recognition, digitization, Spatial sampling
29	Guillaume Burel	Automating Theories in Intuitionistic Logic.	FroCoS	2009	DBLP DOI BibTeX RDF
29	Paul Brauner, Clément Houtmann, Claude Kirchner	Principles of Superdeduction.	LICS	2007	DBLP DOI BibTeX RDF
29	Daniel A. Jiménez, Gabriel H. Loh	Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors.	SBAC-PAD	2006	DBLP DOI BibTeX RDF
29	Andriyan Bayu Suksmono, Astri Handayani, Akira Hirose	Snake in Phase Domain: A Method for Boundary Detection of Objects in Phase Images.	IJCNN	2006	DBLP DOI BibTeX RDF
29	Stéphane Grumbach, Maurizio Rafanelli, Leonardo Tininini	On the equivalence and rewriting of aggregate queries.	Acta Informatica	2004	DBLP DOI BibTeX RDF
29	Christopher Lynch	Schematic Saturation for Decision and Unification Problems.	CADE	2003	DBLP DOI BibTeX RDF
29	Anders Lindström, Michael Nordseth, Lars Bengtsson, Amos Omondi	Arithmetic Circuits Combining Residue and Signed-Digit Representations.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF