Search results for "multi-VTH"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
118	Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari	Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors.	ISPD	2007	DBLP DOI BibTeX RDF	multi-VTH, optimization, timing, low-power design, microprocessor, EDA, leakage power, sizing
43	Takayasu Sakurai	Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control.	ISQED	2000	DBLP DOI BibTeX RDF	VDD, VTH, VLSI, Low-power, CMOS
43	Sherif A. Tawfik, Volkan Kursun	Multi-Vth Level Conversion Circuits for Multi-VDD Systems.	ISCAS	2007	DBLP DOI BibTeX RDF
30	Lih-Yih Chiou, Shien-Chun Luo	An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop.	ISCAS	2007	DBLP DOI BibTeX RDF
25	Vazgen Melikyan, Tigran Hakhverdyan, Sergey Manukyan, Aram Gevorgyan, Davit Babayan	Low power OpenRISC processor with power gating, multi-VTH and multi-voltage techniques.	EWDTS	2016	DBLP DOI BibTeX RDF
23	Theodor Hillebrand, Ludwig Karsthof, Steffen Paul, Dagmar Peters-Drolshagen	Reliability-Aware Multi-Vth Domain Digital Design Assessment.	DDECS	2018	DBLP DOI BibTeX RDF
23	Hao Luo, Mehrdad Heydarzadeh, Mehrdad Nourani	Aging-Leakage Tradeoffs Using Multi-Vth Cell Library.	ATS	2016	DBLP DOI BibTeX RDF
23	Pavan Kumar Bikki, P. Karuppanan	Low power and high performance multi-Vth dual mode logic design.	ICIIS	2016	DBLP DOI BibTeX RDF
23	Chua-Chin Wang, Chia-Lung Hsieh	Disturb-free 5T loadless SRAM cell design with multi-vth transistors using 28 nm CMOS process.	ISOCC	2016	DBLP DOI BibTeX RDF
23	Bo Wang 0020, Jun Zhou 0017, Tony Tae-Hyoung Kim	SRAM devices and circuits optimization toward energy efficiency in multi-Vth CMOS.	Microelectron. J.	2015	DBLP DOI BibTeX RDF
23	Vazgen Melikyan, Eduard Babayan, Anush Melikyan, Davit Babayan, Poghos Petrosyan, Edvard Mkrtchyan	Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor.	EWDTS	2015	DBLP DOI BibTeX RDF
23	Ramesh Nair, Ranga Vemuri	MITH-Dyn: A multi Vth dynamic logic design style using mixed mode FinFETs.	SoCC	2014	DBLP DOI BibTeX RDF
23	Yibo Chen, Yu Wang 0002, Yuan Xie 0001, Andrés Takach	Parametric Yield-Driven Resource Binding in High-Level Synthesis with Multi-Vth/Vdd Library and Device Sizing.	J. Electr. Comput. Eng.	2012	DBLP DOI BibTeX RDF
23	Yibo Chen, Yuan Xie 0001, Yu Wang 0002, Andrés Takach	Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library.	ASP-DAC	2010	DBLP DOI BibTeX RDF
23	Yibo Chen, Yuan Xie 0001, Yu Wang 0002, Andrés Takach	Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment.	ASP-DAC	2010	DBLP DOI BibTeX RDF
23	Abdoul Rjoub, Hassan Almanasrah	Low leakage multi-Vth technique for sequential circuits at transistor level in nanotechnology.	ICECS	2010	DBLP DOI BibTeX RDF
23	Sherif A. Tawfik, Volkan Kursun	Multi-Vth FinFET sequential circuits with independent-gate bias and work-function engineering for reduced power consumption.	APCCAS	2008	DBLP DOI BibTeX RDF
23	Tsuneaki Fuse, Masako Ohta, Motoki Tokumasu, Hiroshige Fujii, Shigeru Kawanaka, Atsushi Kameyama	A 0.5-V power-supply scheme for low-power system LSIs using multi-Vth SOI CMOS technology.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
15	Andrea Calimera, Enrico Macii, Massimo Poncino, R. Iris Bahar	Temperature-insensitive synthesis using multi-vt libraries.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	multi-threshold voltage, temperature-aware, logic synthesis