Search results for "multiclock"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
150	Basant Rajan, R. K. Shyamasundar	Modeling VHDL in Multiclock ESTEREL.	VLSI Design	2000	DBLP DOI BibTeX RDF
103	Gérard Berry, Ellen Sentovich	Multiclock Esterel.	CHARME	2001	DBLP DOI BibTeX RDF
103	Basant Rajan, R. K. Shyamasundar	Multiclock Esterel: A Reactive Framework for Asynchronous Design.	IPDPS	2000	DBLP DOI BibTeX RDF	VHDL, Reactive Systems, Asynchronous System, Synchrony, Esterel
80	Ivan Radojevic, Zoran A. Salcic, Partha S. Roop	McCharts and Multiclock FSMs for modeling large scale systems.	MEMOCODE	2007	DBLP DOI BibTeX RDF
62	Abdoulaye Gamatié, Thierry Gautier	The Signal Synchronous Multiclock Approach to the Design of Distributed Embedded Systems.	IEEE Trans. Parallel Distributed Syst.	2010	DBLP DOI BibTeX RDF	correct-by-construction design methodology, safety-critical domains, asynchronous mechanisms, multiclock, Signal language, Distributed embedded systems, formal validation, synchronous model
59	Malay K. Ganai, Aarti Gupta	Efficient BMC for Multi-Clock Systems with Clocked Specifications.	ASP-DAC	2007	DBLP DOI BibTeX RDF	OpenCores multiclock system benchmarks, clocked specifications, multiphased clocks, level-sensitive latches, SAT-based bounded model checking, synchronous multiclock systems, clocked LTL properties, clock modeling schemes, clock constraints, loop-checks, gated clocks
33	David Biancolin, Albert Magyar, Sagar Karandikar, Alon Amid, Borivoje Nikolic, Jonathan Bachrach, Krste Asanovic	Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim.	IEEE Micro	2021	DBLP DOI BibTeX RDF
33	Naghmeh Karimi, Krishnendu Chakrabarty	Detection, Diagnosis, and Recovery From Clock-Domain Crossing Failures in Multiclock SoCs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2013	DBLP DOI BibTeX RDF
33	Raimon Casanova, Ángel Dieguez, Anna Arbat, Josep Samitier	Multiclock Domain and Dynamic Frequency Scaling Applied to the Control Unit of a Battery Powered for 1 cm3 Microrobot.	J. Low Power Electron.	2006	DBLP DOI BibTeX RDF
33	Atanu Chattopadhyay, Zeljko Zilic	GALDS: a complete framework for designing multiclock ASICs and SoCs.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
33	Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin	GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips.	FPL	2005	DBLP DOI BibTeX RDF
33	Elie Torbey, John P. Knight	Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithms.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
33	Basant Rajan, R. K. Shyamasundar	Modeling Distributed Embedded Systems in Multiclock ESTEREL.	FORTE	2000	DBLP BibTeX RDF
29	Farn Wang, Aloysius K. Mok, E. Allen Emerson	Distributed Real-Time System Specification and Verification in APTL.	ACM Trans. Softw. Eng. Methodol.	1993	DBLP DOI BibTeX RDF	bounded clock rate drifting, multiclock system model, propositional temporal logic, real-time systems, verification, specification, asynchronous
23	Jiang Long, Andrew Seawright, Paparao Kavalipati	Multi-clock SVA synthesis without re-writing.	ASP-DAC	2009	DBLP DOI BibTeX RDF	SVA, multi-clock SVA assertions
23	Abdoulaye Gamatié, Thierry Gautier, Paul Le Guernic, Jean-Pierre Talpin	Polychronous design of embedded real-time applications.	ACM Trans. Softw. Eng. Methodol.	2007	DBLP DOI BibTeX RDF	IMA, Synchronous approach, Signal, Avionics
23	Jean-Pierre Talpin, Dumitru Potop-Butucaru, Julien Ouy, Benoît Caillaud	From multi-clocked synchronous processes to latency-insensitive modules.	EMSOFT	2005	DBLP DOI BibTeX RDF	compositional mapping, separate compilation
23	Farn Wang, Aloysius K. Mok, E. Allen Emerson	Symbolic Model Checking for Distributed Real-Time Systems.	FME	1993	DBLP DOI BibTeX RDF