Search results for "multicycling"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
56	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	ILP models for simultaneous energy and transient power minimization during behavioral synthesis.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	average power, cycle difference power, datapath scheduling, dynamic frequency clocking, multicycling, multiple supply voltages, peak power differential, Peak power
20	Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel Gajski	An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
20	Kaijie Wu 0001, Ramesh Karri	Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
20	Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida	Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis.	DATE	2005	DBLP DOI BibTeX RDF
20	M. A. Ochoa-Montiel, Bashir M. Al-Hashimi, Peter Kollig	Impact of multicycled scheduling on power-area tradeoffs in behavioural synthesis.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
20	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	Peak Power Minimization Through Datapath Scheduling.	ISVLSI	2003	DBLP DOI BibTeX RDF
20	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling.	ICCD	2003	DBLP DOI BibTeX RDF
20	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	Simultaneous peak and average power minimization during datapath scheduling for DSP processors.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	average power, datapath scheduling, dynamic frequency clocking, high-level synthesis, peak power, multiple voltages
20	Apostolos A. Kountouris, Christophe Wolinski	Efficient scheduling of conditional behaviors for high-level synthesis.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	conditional behavior, scheduling, high level synthesis (HLS), Design automation
20	Sanghun Park, Kiyoung Choi	Performance-driven high-level synthesis with bit-level chaining andclock selection.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
20	Chittaranjan A. Mandal, P. P. Chakrabarti 0001, Sujoy Ghose	GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
20	Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha	Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	concurrent error detection, Behavioral synthesis, fault security, fault-tolerant microarchitectures
20	Luiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, J. Van Eijnhoven, Jochen A. G. Jess	A code-motion pruning technique for global scheduling.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	high-level synthesis, code generation, speculative execution, code motion, global scheduling
20	Ashok Halambi, Radu Cornea, Peter Grun, Nikil D. Dutt, Alexandru Nicolau	Architecture Exploration of Parameterizable EPIC SOC Architectures.	DATE	2000	DBLP DOI BibTeX RDF
20	Sandeep Bhatia, Niraj K. Jha	Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
20	Krzysztof Kuchcinski	An Approach to High-Level Synthesis Using Constraint Logic Programming.	EUROMICRO	1998	DBLP DOI BibTeX RDF
20	Anand Raghunathan, Niraj K. Jha	SCALP: an iterative-improvement-based low-power data path synthesis system.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
20	Anand Raghunathan, Niraj K. Jha	An iterative improvement algorithm for low power data path synthesis.	ICCAD	1995	DBLP DOI BibTeX RDF	Low power VLSI design, Power consumption, Behavioral synthesis
20	Christos A. Papachristou, Haluk Konuk	A Linear Program Driven Scheduling and Allocation Method Followed by an Interconnect Optimization Algorithm.	DAC	1990	DBLP DOI BibTeX RDF