Search results for "multiplier-divider"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
116	Hao-Yung Lo, Hsiu-Feng Lin, Chichyang Chen, Jenshiuh Liu, Chia-Cheng Liu	Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	generator, BIST, computer arithmetic, polynomials, VLSI design, multiplication, division
65	Khanittha Kaewdang, Chalermpan Fongsamut, Wanlop Surakampontorn	A wide-band current-mode OTA-based analog multiplier-divider.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
65	David Eisig, Josh Rotstain, Israel Koren	The design of a 64-bit integer multiplier/divider unit.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
58	Marcelo E. Kaihara, Naofumi Takagi	A Hardware Algorithm for Modular Multiplication/Division.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	modular division, cryptography, Computer arithmetic, modular multiplication, redundant representation, hardware algorithm
58	Junhyung Um, Sangwoo Lee, Youngsoo Park, Sungik Jun, Taewhan Kim	An efficient inverse multiplier/divider architecture for cryptography systems.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
45	Gang Li, Brent Maundy	A novel four quadrant CMOS analog multiplier/divider.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
45	Antonio J. López-Martín, Alfonso Carlosena	Geometric-mean based current-mode CMOS multiplier/divider.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
37	Alaaeldin Amin, M. Waleed Shinwari	High-Radix Multiplier-Dividers: Theory, Design, and Hardware.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	quotient digit selection, multiplier-divider, Computer arithmetic, division, SRT
26	Zahra Ebrahimi, Dennis Klar, Mohammad Aasim Ekhtiyar, Akash Kumar 0001	Plasticine: A Cross-layer Approximation Methodology for Multi-kernel Applications through Minimally Biased, High-throughput, and Energy-efficient SIMD Soft Multiplier-divider.	ACM Trans. Design Autom. Electr. Syst.	2022	DBLP DOI BibTeX RDF
26	Predrag Bosko Petrovic	New current-mode RMS-to-DC converters and four-quadrant multiplier/divider based on VDTA.	IET Circuits Devices Syst.	2020	DBLP DOI BibTeX RDF
26	Zahra Ebrahimi, Salim Ullah, Akash Kumar 0001	SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy.	CoRR	2020	DBLP BibTeX RDF
26	Zahra Ebrahimi, Salim Ullah, Akash Kumar 0001	SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy.	ACM Great Lakes Symposium on VLSI	2020	DBLP DOI BibTeX RDF
26	Carlos Aristoteles De la Cruz-Blas, G. Thomas-Erviti, José María Algueta-Miguel, Antonio J. López-Martín	CMOS analogue current-mode multiplier/divider circuit operating in triode-saturation with bulk-driven techniques.	Integr.	2017	DBLP DOI BibTeX RDF
26	Naser Beyraghi, Abdollah Khoei	CMOS implementation of a novel analog multiplier/divider to realize centroid strategy in defuzzifier block.	J. Intell. Fuzzy Syst.	2015	DBLP DOI BibTeX RDF
26	Rodrigo Bispo dos Santos, Paloma Maria Silva Rocha Rizol, Leonardo Mesquita	Design of CMOS current-mode multiplier-divider circuit for type-2 FLC applications.	LASCAS	2015	DBLP DOI BibTeX RDF
26	Thi Hong Tran, Hiroshi Ochi, Yuhei Nagao	A 4 × 4 multiplier-divider-less K-best MIMO decoder up to 2.7 Gbps.	ISCAS	2014	DBLP DOI BibTeX RDF
26	Yuen-Haw Chang	Variable-Conversion-Ratio Switched-Capacitor-Voltage-Multiplier/Divider DC-DC Converter.	IEEE Trans. Circuits Syst. I Regul. Pap.	2011	DBLP DOI BibTeX RDF
26	Pratya Mongkolwai, Worapong Tangsrirat	CFTA-based current multiplier/divider circuit.	ISPACS	2011	DBLP DOI BibTeX RDF
26	Antonio J. López-Martín, Carlos Aristoteles De la Cruz-Blas, Jaime Ramírez-Angulo, Ramón González Carvajal	Compact low-voltage CMOS current-mode multiplier/divider.	ISCAS	2010	DBLP DOI BibTeX RDF
26	Ming-Der Shieh, Jun-Hong Chen, Wen-Ching Lin, Chien-Ming Wu	An Efficient Multiplier/Divider Design for Elliptic Curve Cryptosystem over GF(2m).	J. Inf. Sci. Eng.	2009	DBLP BibTeX RDF
26	Yngvar Berg, Tor Sverre Lande	Ultra low voltage current multiplier/divider.	ICECS	1999	DBLP DOI BibTeX RDF
26	Wei-Shinn Wey, Yu-Chung Huang	A CMOS RMS-to-DC converter using ΣΔ multiplier-divider.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
26	Maria Cristina Piccirilli	A current-conveyor-based multiplier/divider cell.	Int. J. Circuit Theory Appl.	1996	DBLP DOI BibTeX RDF
26	Mohammed Ismail 0001, Robert Brannen, Shigetaka Takagi, Ronny Khan, Oddvar Aaserud, Nobuo Fujii, Nabil I. Khachab	A Configurable CMOS Multiplier/Divider for Analog VLSI.	ISCAS	1993	DBLP BibTeX RDF
26	Alain Guyot, Yvan Herreros, Jean-Michel Muller	JANUS, an on-line multiplier/divider for manipulating large numbers.	IEEE Symposium on Computer Arithmetic	1989	DBLP DOI BibTeX RDF
19	Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura	A fine-grain dynamic sleep control scheme in MIPS R3000.	ICCD	2008	DBLP DOI BibTeX RDF
19	Gang Chen, Guoqiang Bai 0001, Hongyi Chen	A New Systolic Architecture for Modular Division.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Modular division, computer arithmetic, public key cryptosystems, systolic architecture, hardware algorithm
19	Mohammad Fazle Azeem, Asim Baig	Design and Fabrication of Basic Building Blocks For Analog Implementation of Programmable Fuzzy Logic Controller.	IRI	2007	DBLP DOI BibTeX RDF
19	Marcelo E. Kaihara, Naofumi Takagi	A VLSI Algorithm for Modular Multiplication/Division.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
19	Tanes Tanitteerapan, Shinsaku Mori	Simplified input current waveshaping technique by using inductor voltage sensing for power factor correction isolated Sepic rectifier.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
19	Tanes Tanitteerapan, Shinsaku Mori	Fundamental frequency parabolic PWM controller for lossless soft-switching boost power factor correction.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
19	R. Brannen, Hassan O. Elwan, Mohammed Ismail 0001	A simple low-voltage all MOS linear-dB AGC/multiplier circuit.	ISCAS (2)	1999	DBLP DOI BibTeX RDF