Search results for "nanoFabric"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
123	Zhanglei Wang, Krishnendu Chakrabarty	Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	nanofabric, CAEN, chemically assembled, reconfiguration, BIST, nanotechnology, defect tolerance, molecular electronics
113	Kushal Datta, Arindam Mukherjee 0001, Arun Ravindran	Automated design flow for diode-based nanofabrics.	ACM J. Emerg. Technol. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Automatic synmthesis, optimization
68	Mohammad Tehranipoor	Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure.	DFT	2005	DBLP DOI BibTeX RDF
55	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance.	VTS	2006	DBLP DOI BibTeX RDF
33	Jason G. Brown, R. D. (Shawn) Blanton	A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	fault diagnostic accuracy, nanofabrication, regular architectures, nanoFabric, fault diagnosis, logic testing, reconfigurability, integrated circuit testing, fault coverage, nanoelectronics, high defect densities
32	Dawit Burusie Abdi, Shairfe Muhammad Salahuddin, Jürgen Bömmels, Edouard Giacomin, Pieter Weckx, Julien Ryckaert, Geert Hellings, Francky Catthoor	3D SRAM Macro Design in 3D Nanofabric Process Technology.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
32	Edouard Giacomin, Francky Catthoor, Pierre-Emmanuel Gaillardon	Area-Efficient Multiplier Designs Using a 3D Nanofabric Process Flow.	ISCAS	2021	DBLP DOI BibTeX RDF
32	Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon	3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
32	Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon	Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
32	Abdalrahman M. Arafeh, Sadiq M. Sait	Cells reconfiguration around defects in CMOS/nanofabric circuits using simulated evolution heuristic.	ISQED	2015	DBLP DOI BibTeX RDF
32	Sadiq M. Sait, Abdalrahman M. Arafeh	Tabu search based cells placement in nanofabric architectures with restricted connectivity.	ISQED	2013	DBLP DOI BibTeX RDF
32	J. G. Alzate, Parag Upadhyaya, M. Lewis, J. Nath, Y. T. Lin, Kin Wong, S. Cherepov, P. Khalili Amiri, Kang L. Wang, J. Hockel, A. Bur, G. P. Carman, S. Bender, Y. Tserkovnyak, J. Zhu, Y.-J. Chen, I. N. Krivorotov, J. Katine, J. Langer, Prasad Shabadi, Santosh Khasanvis, Sankara Narayanan Rajapandian, Csaba Andras Moritz, Alexander Khitun	Spin wave nanofabric update.	NANOARCH	2012	DBLP DOI BibTeX RDF
32	Prasad Shabadi, Alexander Khitun, Kin Wong, P. Khalili Amiri, Kang L. Wang, Csaba Andras Moritz	Spin wave functions nanofabric update.	NANOARCH	2011	DBLP DOI BibTeX RDF
32	Stefano Frache, Luca Gaetano Amarù, Mariagrazia Graziano, Maurizio Zamboni	Nanofabric power analysis: Biosequence alignment case study.	NANOARCH	2011	DBLP DOI BibTeX RDF
32	Mandar V. Joshi, Waleed Al-Assadi	Nanofabric PLA Architecture with Double Variable Redundancy.	CDES	2007	DBLP BibTeX RDF
32	Mandar V. Joshi, Waleed Al-Assadi	Nanofabric PLA architecture with Redundancy Enhancement.	DFT	2007	DBLP DOI BibTeX RDF
32	Jason G. Brown, R. D. (Shawn) Blanton	CAEN-BIST: Testing the NanoFabric.	ITC	2004	DBLP DOI BibTeX RDF
23	Mohammad Tehranipoor, Reza M. Rad	Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based Nanofabrics.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
23	Chen He, Margarida F. Jacome	Defect-Aware High-Level Synthesis Targeted at Reconfigurable Nanofabrics.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
23	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Towards Nanoelectronics Processor Architectures.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	fault tolerance, reliability, computational model, processor architecture, nanoelectronics, time redundancy, hardware redundancy
23	Hossein Asadi 0001, Mehdi Baradaran Tahoori, Chandra Tirumurti	Estimating Error Propagation Probabilities with Bounded Variances.	DFT	2007	DBLP DOI BibTeX RDF
23	Mohammad Tehranipoor, Reza M. Rad	Test and recovery for fine-grained nanoscale architectures.	FPGA	2006	DBLP DOI BibTeX RDF
23	Chen He, Margarida F. Jacome	RAS-NANO: a reliability-aware synthesis framework for reconfigurable nanofabrics.	DATE	2006	DBLP DOI BibTeX RDF