Search results for "on-chip-memory"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
63	Mohamed Shalan, Vincent John Mooney III	Hardware support for real-time embedded multiprocessor system-on-a-chip memory management.	CODES	2002	DBLP DOI BibTeX RDF	Atalanta, SoCDMMU, real-time operating systems., two-level memory management, real-time systems, embedded systems, System-on-a-Chip, dynamic memory management
60	Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau	On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	system design, data cache, data partitioning, system synthesis, scratch-pad memory, on-chip memory, memory synthesis
50	Jeonghun Cho, Yunheung Paek	Run-Time Memory Optimization for DDMB Architecture Through a CCB Algorithm.	EUC Workshops	2006	DBLP DOI BibTeX RDF	dual data memory banks, compiler and on-chip memory, DSP, Run-time environment
47	Heeyeol Yu, Rabi N. Mahapatra	A Memory-Efficient Hashing by Multi-Predicate Bloom Filters for Packet Classification.	INFOCOM	2008	DBLP DOI BibTeX RDF
44	Abhijit Chatterjee, Peeter Ellervee, Vincent John Mooney III, Jun-Cheol Park, Kyu-won Choi, Kiran Puttaswamy	System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory.	ISSS	2002	DBLP DOI BibTeX RDF	voltage/frequency scaling, embedded systems, design space, power-performance trade-offs
42	Mahmut T. Kandemir, Ozcan Ozturk 0001, Mustafa Karaköy	Dynamic on-chip memory management for chip multiprocessors.	CASES	2004	DBLP DOI BibTeX RDF	chip multiprocessors, optimizing compiler, memory bank
40	Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, Daisuke Takahashi, Hiroshi Nakamura, Mitsuhisa Sato	SCIMA-SMP: on-chip memory processor architecture for SMP.	WMPI	2004	DBLP DOI BibTeX RDF
40	Motonobu Fujita, Masaaki Kondo, Hiroshi Nakamura	Data Movement Optimization for Software-Controlled On-Chip Memory.	Interaction between Compilers and Computer Architectures	2004	DBLP DOI BibTeX RDF
39	Xuehong Sun, Yiqiang Q. Zhao	An On-Chip IP Address Lookup Algorithm.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Algorithms, hardware, tree data structures, range search, on-chip memory, IP address lookup
38	Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin, Suleyman Tosun	Multi-Level On-Chip Memory Hierarchy Design for Embedded Chip Multiprocessors.	ICPADS (1)	2006	DBLP DOI BibTeX RDF
37	Lei Wang, Santosh Pande	Data I/O Minimization for Loops on Limited Onchip Memory Processors.	LCPC	1999	DBLP DOI BibTeX RDF
36	Noel Eisley, Li-Shiuan Peh, Li Shang	Leveraging on-chip networks for data cache migration in chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	network-driven computing, interconnection network, CMP, chip-multiprocessor, migration
36	Ross McIlroy, Peter Dickman, Joe Sventek	Efficient dynamic heap allocation of scratch-pad memory.	ISMM	2008	DBLP DOI BibTeX RDF	on-core memory, concurrency, memory management
36	Radomir Jakovljevic, Aleksandar Beric	N-meander scanning trace a method for the on-chip bandwidth reduction.	ICIP	2008	DBLP DOI BibTeX RDF
36	Hakduran Koc, Mahmut T. Kandemir, Ehat Ercanli, Ozcan Ozturk 0001	Reducing Off-Chip Memory Access Costs Using Data Recomputation in Embedded Chip Multi-processors.	DAC	2007	DBLP DOI BibTeX RDF
36	Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau	Exploiting off-chip memory access modes in high-level synthesis.	ICCAD	1997	DBLP DOI BibTeX RDF	High Level Synthesis, DRAM, Memory Synthesis
35	Edgar G. Daylight, Sven Wuytack, Chantal Ykman-Couvreur, Francky Catthoor	Analyzing energy friendly steady state phases of dynamic application execution in terms of sparse data structures.	ISLPED	2002	DBLP DOI BibTeX RDF	on-chip memory footprint, partitioned data structure, energy consumption
35	Hoseok Chang, Junho Cho, Wonyong Sung	Compiler-Based Performance Evaluation of an SIMD Processor with a Multi-Bank Memory Unit.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Multi-bank memory, Vectorizing compiler, Data allocation, On-chip memory, SIMD processor
35	Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin	Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	data compression, chip multiprocessors, optimizing compiler
34	Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung	Automatic On-chip Memory Minimization for Data Reuse.	FCCM	2007	DBLP DOI BibTeX RDF
33	Ozcan Ozturk 0001, Mahmut T. Kandemir, G. Chen, Mary Jane Irwin, Mustafa Karaköy	Customized on-chip memories for embedded chip multiprocessors.	ASP-DAC	2005	DBLP DOI BibTeX RDF
33	Preeti Ranjan Panda, Nikil D. Dutt	Low-power memory mapping through reducing address bus activity.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
31	Victor De La Luz, Mahmut T. Kandemir, Ugur Sezer	Improving Off-Chip Memory Energy Behavior in a Multi-processor, Multi-bank Environment.	LCPC	2001	DBLP DOI BibTeX RDF
31	Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau	Incorporating DRAM access modes into high-level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
31	Chenjie Yu, Peter Petrov	Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms.	DAC	2010	DBLP DOI BibTeX RDF	L2 cache partitioning, off-chip bandwidth reduction
31	Heeyeol Yu, Rabi N. Mahapatra	A space- and time-efficient hash table hierarchically indexed by Bloom filters.	IPDPS	2008	DBLP DOI BibTeX RDF
31	Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere	Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips.	FPL	2007	DBLP DOI BibTeX RDF
30	Shuo Wang, Lei Wang 0003	Exploiting soft redundancy for error-resilient on-chip memory design.	ICCAD	2006	DBLP DOI BibTeX RDF	cache space utilization, memory system, error tolerance
30	Vijay Nagarajan, Rajiv Gupta 0001, Arvind Krishnaswamy	Compiler-Assisted Memory Encryption for Embedded Processors.	Trans. High Perform. Embed. Archit. Compil.	2009	DBLP DOI BibTeX RDF
30	Hiroshi Nakamura, Masaaki Kondo, Taisuke Boku	Software Controlled Reconfigurable On-Chip Memory for High Performance Computing.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
29	Jason E. Fritts, Roger D. Chamberlain	Breaking the Memory Bottleneck with an Optical Data Path.	Annual Simulation Symposium	2002	DBLP DOI BibTeX RDF	bandwidth bottleneck, processor-memory gap, performance evaluation, media processing, optical bus
28	Gang Qu 0001, Miodrag Potkonjak	System synthesis of synchronous multimedia applications.	ACM Trans. Embed. Comput. Syst.	2003	DBLP DOI BibTeX RDF	high-level embedded systems synthesis, on-chip memory minimization, synchronization
28	Edgar G. Daylight, T. Fermentel, Chantal Ykman-Couvreur, Francky Catthoor	Incorporating energy efficient data structures into modular software implementations for internet-based embedded systems.	Workshop on Software and Performance	2002	DBLP DOI BibTeX RDF	on-chip memory footprint, partitioned data structure, energy consumption
28	Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken V. Vu, Xiaowei Jiang, Yan Solihin	Scaling the bandwidth wall: challenges in and avenues for CMP scaling.	ISCA	2009	DBLP DOI BibTeX RDF	analytical model, memory bandwidth, chip multi-processor
28	Victor M. DeLaLuz, Ismail Kadayif, Mahmut T. Kandemir, Ugur Sezer	Access Pattern Restructuring for Memory Energy.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	banked memories, embedded systems, Compiler optimization, energy consumption, access pattern
27	Rajeshwari Banakar, Stefan Steinke, Bo-Sik Lee, M. Balakrishnan, Peter Marwedel	Scratchpad memory: design alternative for cache on-chip memory in embedded systems.	CODES	2002	DBLP DOI BibTeX RDF	Cactis, SCRATCHPAD
27	Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh	Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design.	DATE	2003	DBLP DOI BibTeX RDF
27	Ruirui C. Huang, G. Edward Suh	IVEC: off-chip memory integrity protection for both security and reliability.	ISCA	2010	DBLP DOI BibTeX RDF	security, fault tolerance, reliability, error detection, error correction, memory systems
27	Chih-Chi Cheng, Chao-Tsung Huang, Ching-Yeh Chen, Chung-Jr Lian, Liang-Gee Chen	On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform.	IEEE Trans. Circuits Syst. Video Technol.	2007	DBLP DOI BibTeX RDF
27	Ling Ming, Zhang Yu, Shen Lin 0002	An Alternative Choice of Scratch-Pad Memory for Energy Optimization in Embedded System.	ICNSC	2008	DBLP DOI BibTeX RDF
27	Vijay Nagarajan, Rajiv Gupta 0001, Arvind Krishnaswamy	Compiler-Assisted Memory Encryption for Embedded Processors.	HiPEAC	2007	DBLP DOI BibTeX RDF
27	Mahmut T. Kandemir, J. Ramanujam, Mary Jane Irwin, Narayanan Vijaykrishnan, Ismail Kadayif, Amisha Parikh	A compiler-based approach for dynamically managing scratch-pad memories in embedded systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
26	Abhishek Das, William J. Dally, Peter R. Mattson	Compiling for stream processing.	PACT	2006	DBLP DOI BibTeX RDF	SRF allocation, Stream Operation Precedence (SOP) graph, StreamC, coarse-grained operations, producer-consumer locality, scoreboard slot assignment, stream scheduling, strip-mining, software-pipelining, task level parallelism, stream programming model
26	Ozcan Ozturk 0001, G. Chen, Mahmut T. Kandemir, Mustafa Karaköy	An Integer Linear Programming Based Approach to Simultaneous Memory Space Partitioning and Data Allocation for Chip Multiprocessors.	ISVLSI	2006	DBLP DOI BibTeX RDF
26	Per Stenström	Chip-multiprocessing and beyond.	HPCA	2006	DBLP DOI BibTeX RDF
26	Chunhui Zhang, Fadi J. Kurdahi	Reducing Off-Chip Memory Access via Stream-Conscious Tiling on Multimedia Applications.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	low power, DSP, memory hierarchy, tiling, data locality, iteration space
26	Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose	Logic synthesis for a single large look-up table.	ICCD	1995	DBLP DOI BibTeX RDF	single large look-up table, LUT-based field-programmable gate array architectures, simulation time minimisation, compile-code, software simulation, field programmable gate arrays, Boolean function, logic design, logic synthesis, hardware accelerator, programmable logic arrays, table lookup, logic simulation, FPGA architectures, logic functions, on-chip memory, memory constraint
26	Mahmut T. Kandemir	Reducing energy consumption of multiprocessor SoC architectures by exploiting memory bank locality.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Banked memory systems, bank locality, compiler optimization, energy consumption, multiprocessor SoC
26	Mahmut T. Kandemir	Exploiting Memory Bank Locality in Multiprocessor SoC Architectures.	IPDPS	2004	DBLP DOI BibTeX RDF
25	Preeti Ranjan Panda	Memory bank customization and assignment in behavioral synthesis.	ICCAD	1999	DBLP DOI BibTeX RDF
25	Woo-Cheol Kwon, Sung-Min Hong, Sungjoo Yoo, Byeong Min, Kyu-Myung Choi, Soo-Kwan Eo	An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication.	DATE	2008	DBLP DOI BibTeX RDF
25	Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau	Efficient utilization of scratch-pad memory in embedded processor applications.	ED&TC	1997	DBLP DOI BibTeX RDF
25	Derek Chiou, Prabhat Jain, Larry Rudolph, Srinivas Devadas	Application-specific memory management for embedded systems using software-controlled caches.	DAC	2000	DBLP DOI BibTeX RDF
24	Pier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini	SHAPES: : a tiled scalable software hardware architecture platform for embedded systems.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	MP-SOC, distributed network processors, hardware dependent software, network of processes, tiled parallel architectures, simulation, scheduling, embedded systems, VLIW, RISC, model based design, binding, retargetable compiler, application mapping
24	Evan Speight, Hazim Shafi, Lixin Zhang 0002, Ramakrishnan Rajamony	Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors.	ISCA	2005	DBLP DOI BibTeX RDF
24	Hoseok Chang, Wonyong Sung	Access-Pattern-Aware On-Chip Memory Allocation for SIMD Processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
24	Waibhav Tembe, Santosh Pande	Loop Restructuring for Data I/O Minimization on Limited On-Chip Memory Embedded Processors.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	embedded processors, data locality, program dependence graph, Loop fusion, limited memory
24	Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan	A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	sequential access buffer, media benchmark, flexible sequential and random access memory, on-chip memory
24	Erik G. Hallnor, Steven K. Reinhardt	A Unified Compressed Memory Hierarchy.	HPCA	2005	DBLP DOI BibTeX RDF
24	Per Stenström	The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges.	HiPEAC	2005	DBLP DOI BibTeX RDF
24	T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravikumar	Optimal Code and Data Layout in Embedded Systems.	VLSI Design	2003	DBLP DOI BibTeX RDF
23	Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward A. Lee	Optimized software synthesis for synchronous dataflow.	ASAP	1997	DBLP DOI BibTeX RDF	optimized software synthesis, programmable digital signal processors, off-chip memory, real-time systems, digital signal processing, synchronous dataflow, graphical programs
23	Muthu Manikandan Baskaran, Uday Bondhugula, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan	Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories.	PPoPP	2008	DBLP DOI BibTeX RDF	graphics processor unit, multi-level tiling, scratchpad memory, data movement
23	Isabelle Puaut, Christophe Pais	Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison.	DATE	2007	DBLP DOI BibTeX RDF
23	Jingling Xue	Compiler-Directed Scratchpad Memory Management.	ICESS	2005	DBLP DOI BibTeX RDF
22	Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis 0001	Designing Low-Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip Memory.	PATMOS	2005	DBLP DOI BibTeX RDF
22	Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung	Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
22	Magnus Jahre, Marius Grannæs, Lasse Natvig	A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures.	HPCC	2009	DBLP DOI BibTeX RDF
22	Sailesh Kumar, Jonathan S. Turner, Patrick Crowley	Peacock Hashing: Deterministic and Updatable Hashing for High Performance Networking.	INFOCOM	2008	DBLP DOI BibTeX RDF
22	Haoyu Song 0001, Murali S. Kodialam, Fang Hao, T. V. Lakshman	Scalable IP Lookups using Shape Graphs.	ICNP	2009	DBLP DOI BibTeX RDF
21	Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kandemir, Mustafa Karaköy, Mary Jane Irwin	Integrated code and data placement in two-dimensional mesh based chip multiprocessors.	ICCAD	2008	DBLP DOI BibTeX RDF
21	Amin Firoozshahian, Alex Solomatnikov, Ofer Shacham, Zain Asgar, Stephen Richardson, Christos Kozyrakis, Mark Horowitz	A memory system design framework: creating smart memories.	ISCA	2009	DBLP DOI BibTeX RDF	memory access protocol, protocol controller, transactional memory, reconfigurable architecture, cache coherence, memory systems, multi-core processors, stream programming
21	Tung-Chien Chen, Chuan-Yung Tsai, Yu-Wen Huang, Liang-Gee Chen	Single Reference Frame Multiple Current Macroblocks Scheme for Multiple Reference Frame Motion Estimation in H.264/AVC.	IEEE Trans. Circuits Syst. Video Technol.	2007	DBLP DOI BibTeX RDF
21	Simone Medardoni, Martino Ruggiero, Davide Bertozzi, Luca Benini, Giovanni Strano, Carlo Pistritto	Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms.	DATE	2007	DBLP DOI BibTeX RDF
21	Ke Ning, David R. Kaeli	Bus Power Estimation and Power-Efficient Bus Arbitration for System-on-a-Chip Embedded Systems.	PACS	2004	DBLP DOI BibTeX RDF	Embedded System, Power-Aware, External Memory, Media Processor, Bus Arbitration
21	Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye, David Duarte	Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	simulation, optimizations, energy models, Energy estimation
21	Steven Trimberger, Dean Carberry, Anders Johnson, Jennifer Wong	A time-multiplexed FPGA.	FCCM	1997	DBLP DOI BibTeX RDF
21	Hoang Le, Yi-Hua E. Yang, Viktor K. Prasanna	Memory efficient string matching: a modular approach on FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	deep packet classification, fpga, packet filtering
21	Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis	A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
21	Hanene Ben Fradj, Asmaa el Ouardighi, Cécile Belleudy, Michel Auguin	Energy aware memory architecture configuration.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
21	Anand Ramachandran, Margarida F. Jacome	Xtream-fit: an energy-delay efficient data memory subsystem for embedded media processing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
20	David Whelihan, Herman Schmit	Memory optimization in single chip network switch fabrics.	DAC	2002	DBLP DOI BibTeX RDF	network switch, SOC, memory optimization
20	Radomir Jakovljevic, Aleksandar Beric	A method for improving the efficiency of a two-level memory hierarchy.	SiPS	2008	DBLP DOI BibTeX RDF
20	Yanqin Yang, Zili Shao, Linfeng Pan, Minyi Guo	ISOS: Space Overlapping Based on Iteration Access Patterns for Dynamic Scratch-pad Memory Management in Embedded Systems.	ICYCS	2008	DBLP DOI BibTeX RDF
20	Bas Breijer, Filipa Duarte, Stephan Wong	An OCM based shared Memory controller for Virtex 4.	FPL	2007	DBLP DOI BibTeX RDF
20	Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin	BB-GC: Basic-Block Level Garbage Collection.	DATE	2005	DBLP DOI BibTeX RDF
20	Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang	Fail Pattern Identification for Memory Built-In Self-Repair.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
20	Duo Ding, David Z. Pan	OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture.	SLIP	2009	DBLP DOI BibTeX RDF	photonic networks-on-chip, low power, computer aided design, high performance
20	Ken Kennedy	Software Challenges for Multicore Computing.	HiPC	2006	DBLP DOI BibTeX RDF
20	Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar	Optimizing Replication, Communication, and Capacity Allocation in CMPs.	ISCA	2005	DBLP DOI BibTeX RDF
19	Mary W. Hall, Craig S. Steele	Memory Management in a PIM-Based Architecture.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
19	Martin Zabel, Rainer G. Spallek	Application requirements and efficiency of embedded Java bytecode multi-cores.	JTRES	2010	DBLP DOI BibTeX RDF	multi-core, multi-threaded, realtime, Java bytecode
19	Marcos Sánchez-Élez, Milagros Fernández, Manuel L. Anido, Haitao Du, Nader Bagherzadeh, Román Hermida	Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures.	DATE	2003	DBLP DOI BibTeX RDF
19	Liesbeth Steffens, Manvi Agarwal, Pieter van der Wolf	Real-Time Analysis for Memory Access in Media Processing SoCs: A Practical Approach.	ECRTS	2008	DBLP DOI BibTeX RDF
19	Xi Chen 0068, Robert P. Dick, Alok N. Choudhary	Operating System Controlled Processor-Memory Bus Encryption.	DATE	2008	DBLP DOI BibTeX RDF
19	Yonggang Che	Evaluating the Data Access Efficiency of Imagine Stream Processor with Scientific Applications.	ICYCS	2008	DBLP DOI BibTeX RDF
19	Martin Thuresson, Per Stenström	Accommodation of the Bandwidth of Large Cache Blocks Using Cache/Memory Link Compression.	ICPP	2008	DBLP DOI BibTeX RDF
19	T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan	Memory Architecture Exploration Framework for Cache Based Embedded SOC.	VLSI Design	2008	DBLP DOI BibTeX RDF
19	T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan	MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip.	ASP-DAC	2007	DBLP DOI BibTeX RDF
19	Sarang Dharmapurikar, John W. Lockwood	Fast and Scalable Pattern Matching for Network Intrusion Detection Systems.	IEEE J. Sel. Areas Commun.	2006	DBLP DOI BibTeX RDF