Search results for "placer"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
104	Andrew B. Kahng, Qinke Wang	Implementation and extensibility of an analytic placer.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
90	Andrew B. Kahng, Qinke Wang	Implementation and extensibility of an analytic placer.	ISPD	2004	DBLP DOI BibTeX RDF	I/O-Core co-placement, hierarchical placement, congestion, geometric constraints, analytical placement
81	David A. Papa, Saurabh N. Adya, Igor L. Markov	Constructive benchmarking for placement.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	placer, performance, evaluation, benchmark, comparison
79	Andrew B. Kahng, Sherief Reda	Evaluation of placer suboptimality via zero-change netlist transformations.	ISPD	2005	DBLP DOI BibTeX RDF	placer suboptimality, benchmarking, wirelength
66	Peter Spindler, Frank M. Johannes	Fast and accurate routing demand estimation for efficient routability-driven placement.	DATE	2007	DBLP DOI BibTeX RDF
66	Saurabh N. Adya, Igor L. Markov	Combinatorial techniques for mixed-size placement.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	VLSI, placement, floorplanning
55	Habib Youssef, Sadiq M. Sait, Khaled Nassar, Muhammad S. T. Benten	Performance driven standard-cell placement using the genetic algorithm.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	connection length, timing-driven placer, /spl alpha/-criticality, delay performance improvement, genetic algorithms, genetic algorithm, delays, timing, logic CAD, circuit layout CAD, cellular arrays, integrated circuit layout, critical paths, area, propagation delays, wire length, timing performance, IC design, standard-cell placement
53	Shantanu Dutt, Huan Ren, Fenghua Yuan, Vishal Suthar	A network-flow approach to timing-driven incremental placement for ASICs.	ICCAD	2006	DBLP DOI BibTeX RDF
53	Peter Spindler, Frank M. Johannes	Fast and robust quadratic placement combined with an exact linear net model.	ICCAD	2006	DBLP DOI BibTeX RDF
53	Dilvan de Abreu Moreira, Les T. Walczowski	AGENTS a distributed client-server system for leaf cell generation.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	genetic algorithms, software agents, client/server model
51	Kristofer Vorwerk, Andrew A. Kennings, Anthony Vannelli	Engineering details of a stable force-directed placer.	ICCAD	2004	DBLP DOI BibTeX RDF
49	Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang 0012	AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA.	CoRR	2022	DBLP DOI BibTeX RDF
49	Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang 0012	AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA.	ICCAD	2021	DBLP DOI BibTeX RDF
49	Nima Karimpour Darav, Andrew A. Kennings, Aysa Fakheri Tabrizi, David T. Westwick, Laleh Behjat	Eh?Placer: A High-Performance Modern Technology-Driven Placer.	ACM Trans. Design Autom. Electr. Syst.	2016	DBLP DOI BibTeX RDF
40	Huimin Bian, Andrew C. Ling, Alexander Choong, Jianwen Zhu	Towards scalable placement for FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, convex optimization, quadratic placement, bipartite matching
40	Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Few-Juh Huang, T.-Y. Liu	MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
40	Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu	MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs.	DAC	2007	DBLP DOI BibTeX RDF
40	Andrew B. Kahng, Sherief Reda	Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
40	Bo Hu 0006, Malgorzata Marek-Sadowska	Multilevel fixed-point-addition-based VLSI placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
40	Mongkol Ekpanyapong, Michael B. Healy, Sung Kyu Lim	Placement for configurable dataflow architecture.	ASP-DAC	2005	DBLP DOI BibTeX RDF
40	Bo Hu 0006, Malgorzata Marek-Sadowska	Fine granularity clustering-based placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
40	Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich	Task scheduling for heterogeneous reconfigurable computers.	SBCCI	2004	DBLP DOI BibTeX RDF	hardware preemption, scheduling, FPGA, placement, reconfigurable computing, partial reconfiguration
40	Bo Hu 0006, Malgorzata Marek-Sadowska	Multilevel expansion-based VLSI placement with blockages.	ICCAD	2004	DBLP DOI BibTeX RDF
40	Pak K. Chan, Martine D. F. Schlag	Parallel placement for field-programmable gate arrays.	FPGA	2003	DBLP DOI BibTeX RDF	parallel placement, FPGAs, timing-driven placement, analytical placement
40	Qinghua Liu, Bo Hu 0006, Malgorzata Marek-Sadowska	Wire length prediction in constraint driven placement.	SLIP	2003	DBLP DOI BibTeX RDF	wire length prediction, clustering
40	Bill Halpin, Naresh Sehgal, C. Y. Roger Chen	Detailed Placement with Net Length Constraints.	IWSOC	2003	DBLP DOI BibTeX RDF
40	Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh	Routability driven white space allocation for fixed-die standard-cell placement.	ISPD	2002	DBLP DOI BibTeX RDF	placement, physical design, routability
39	Pedro Soto-Acosta, Emilio Placer-Maruri, Daniel Perez González	A case analysis of a product lifecycle information management framework for SMEs.	Int. J. Inf. Manag.	2016	DBLP DOI BibTeX RDF
39	Mitja Placer, Stanislav Kovacic	Enhancing Indoor Inertial Pedestrian Navigation Using a Shoe-Worn Marker.	Sensors	2013	DBLP DOI BibTeX RDF
39	Cástor Mariño, Manuel G. Penedo, Simón Pena Placer, F. González	Crest Line and Correlation Filter Based Location of the Macula in Digital Retinal Images.	BIOSIGNALS (2)	2008	DBLP BibTeX RDF
39	John Placer, Assim Sagahyroon	Design and Implementation of a VSL System.	Intell. Autom. Soft Comput.	2007	DBLP DOI BibTeX RDF
39	John Placer, C. N. Slobodchikoff	Developing New Metrics for the Investigation of Animal Vocalizations.	Intell. Autom. Soft Comput.	2001	DBLP DOI BibTeX RDF
39	Jordi Atserias Batalla, Josep Carmona Vargas, Irene Castellón Masalles, Sergi Cervell, Montserrat Civit Torruella, Lluís Màrquez, Maria Antònia Martí Antonín, Lluís Padró Cirera, Roberto Placer, Horacio Rodríguez Hontoria, Mariona Taulé Delor, Jordi Turmo	Morphosyntactic analysis and parsing of unrestricted Spanish text.	LREC	1998	DBLP BibTeX RDF
39	Josep Carmona Vargas, Sergi Cervell, Lluís Màrquez, Maria Antònia Martí, Lluís Padró Cirera, Roberto Placer, Horacio Rodríguez, Mariona Taulé Delor, Jordi Turmo	An environment for mophosyntactic processing of unrestricted Spanish text.	LREC	1998	DBLP BibTeX RDF
39	John Placer	The Promise of Multiparadigm Languages as Pedagogical Tools.	ACM Conference on Computer Science	1993	DBLP DOI BibTeX RDF
39	John Placer	Integrating destructive assignment and lazy evaluation in the multiparadigm language G-2.	ACM SIGPLAN Notices	1992	DBLP DOI BibTeX RDF
39	John Placer	Multiparadigm research: a new direction of language design.	ACM SIGPLAN Notices	1991	DBLP DOI BibTeX RDF
39	John Placer	The Multiparadigm Language G.	Comput. Lang.	1991	DBLP DOI BibTeX RDF
37	Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang	NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
37	Natarajan Viswanathan, Min Pan, Chris C. N. Chu	FastPlace 2.0: an efficient analytical placer for mixed-mode designs.	ASP-DAC	2006	DBLP DOI BibTeX RDF
37	Zhe-Wei Jiang, Tung-Chieh Chen, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang	NTUplace2: a hybrid placer using partitioning and analytical techniques.	ISPD	2006	DBLP DOI BibTeX RDF	placement, physical design, legalization
37	Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang	A high-quality mixed-size analytical placer considering preplaced blocks and density constraints.	ICCAD	2006	DBLP DOI BibTeX RDF
37	Andrew B. Kahng, Qinke Wang	An analytic placer for mixed-size placement and timing-driven placement.	ICCAD	2004	DBLP DOI BibTeX RDF
37	Chi-Ming Tsai, Kun-Tien Kuo, Chyi-Hui Hong, Rung-Bin Lin	An Adaptive Interconnect-Length Driven Placer.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
37	Gang Huang, Xianlong Hong, Changge Qiao, Yici Cai	A Timing-Driven Block Placer Based on Sequence Pair Model.	ASP-DAC	1999	DBLP DOI BibTeX RDF	timing-driven, building block placement, sequence pair, simulated annealing algorithm
28	Andrew B. Kahng, Sherief Reda	A tale of two nets: studies of wirelength progression in physical design.	SLIP	2006	DBLP DOI BibTeX RDF	placer suboptimality, benchmarking, consistency, similarity, wirelength
28	Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden	Benchmarking for large-scale placement and beyond.	ISPD	2003	DBLP DOI BibTeX RDF	placer, signal delay, performance, evaluation, routing, benchmark, timing, placement, layout, congestion, comparison, wirelength
26	Zigang Xiao, Evangeline F. Y. Young	Droplet-routing-aware module placement for cross-referencing biochips.	ISPD	2010	DBLP DOI BibTeX RDF	cross-referencing, dmfb, synthesis, placement, microfluidics, biochip
26	Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li 0001, Charles J. Alpert, Shyam Ramji, Chris Chu	ITOP: integrating timing optimization within placement.	ISPD	2010	DBLP DOI BibTeX RDF	placement, timing optimization, physical synthesis
26	Jason Cong, Guojie Luo	A multilevel analytical placement for 3D ICs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
26	Hangpei Tian, Deyuan Gao, Wu Wei, Xiaoya Fan, Yian Zhu	Improving Performance of Partial Reconfiguration Using Strategy of Virtual Deletion.	FCCM	2008	DBLP DOI BibTeX RDF
26	Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan	Guiding global placement with wire density.	ICCAD	2008	DBLP DOI BibTeX RDF
26	Hsin-Chen Chen, Yi-Lin Chuang, Yao-Wen Chang, Yung-Chung Chang	Constraint graph-based macro placement for modern mixed-size circuit designs.	ICCAD	2008	DBLP DOI BibTeX RDF
26	Chen Li 0004, Min Xie 0004, Cheng-Kok Koh, Jason Cong, Patrick H. Madden	Routability-Driven Placement and White Space Allocation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
26	Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis 0001	3D-Vias Aware Quadratic Placement for 3D VLSI Circuits.	ISVLSI	2007	DBLP DOI BibTeX RDF
26	Andrew A. Kennings, Kristofer Vorwerk	Force-Directed Methods for Generic Placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
26	Andrew B. Kahng, Qinke Wang	A faster implementation of APlace.	ISPD	2006	DBLP DOI BibTeX RDF	lens aberration, supply voltage degradation, scalability, analytical placement
26	Tony F. Chan, Jason Cong, Joseph R. Shinnerl, Kenton Sze, Min Xie 0004	mPL6: enhanced multilevel mixed-size placement.	ISPD	2006	DBLP DOI BibTeX RDF	mixed-size placement, legalization, Helmholtz equation, force-directed placement, multilevel optimization
26	Zhong Xiu, David A. Papa, Philip Chong, Christoph Albrecht, Andreas Kuehlmann, Rob A. Rutenbar, Igor L. Markov	Early research experience with OpenAccess gear: an open source development environment for physical design.	ISPD	2005	DBLP DOI BibTeX RDF	database, timing, open source, placement, physical design, EDA
26	Qinghua Liu, Malgorzata Marek-Sadowska	A congestion-driven placement framework with local congestion prediction.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	cell padding, congestion prediction, placement migration
26	Andrew B. Kahng, Igor L. Markov, Sherief Reda	Boosting: Min-Cut Placement with Improved Signal Delay.	DATE	2004	DBLP DOI BibTeX RDF
26	Satrajit Chatterjee, Robert K. Brayton	A new incremental placement algorithm and its application to congestion-aware divisor extraction.	ICCAD	2004	DBLP DOI BibTeX RDF
26	Bo Hu 0006, Malgorzata Marek-Sadowska	Fine granularity clustering for large scale placement problems.	ISPD	2003	DBLP DOI BibTeX RDF	clustering, placement
26	Saurabh N. Adya, Igor L. Markov, Paul Villarrubia	On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis.	ICCAD	2003	DBLP DOI BibTeX RDF
26	Saurabh N. Adya, Igor L. Markov	Consistent placement of macro-blocks using floorplanning and standard-cell placement.	ISPD	2002	DBLP DOI BibTeX RDF
26	Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh	A Standard-Cell Placement Tool for Designs with High Row Utilization.	ICCD	2002	DBLP DOI BibTeX RDF
26	Ranjit K. Dash, T. Pramod, Vinita Vasudevan, M. Ramakrishna 0001	A Transistor Level Placement Tool for Custom Cell Generation.	VLSI Design	2000	DBLP DOI BibTeX RDF	simulated annealing, placement
26	Shigetoshi Nakatake, Yoji Kajitani	Channel-driven global routing with consistent placement (extended abstract).	ICCAD	1994	DBLP DOI BibTeX RDF
24	Andrew B. Kahng, Ravi Varadarajan, Zhiang Wang	Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-Scale Complex IP Blocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
24	Pranav Jain, Gagandeep, Sneh Saurabh	FLIP: An Artificial Neural Network-based Post-routing Incremental Placer.	VLSID	2024	DBLP DOI BibTeX RDF
24	Zhili Xiong, Rachel Selina Rajarathnam, Zhixing Jiang, Hanqing Zhu, David Z. Pan	DREAMPlaceFPGA-MP: An Open-Source GPU-Accelerated Macro Placer for Modern FPGAs with Cascade Shapes and Region Constraints.	CoRR	2023	DBLP DOI BibTeX RDF
24	Andrew B. Kahng, Ravi Varadarajan, Zhiang Wang	Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-scale Complex IP Blocks.	CoRR	2023	DBLP DOI BibTeX RDF
24	Josef Grus, Zdenek Hanzálek, Dalibor Barri, Patrik Vacula	Automatic Placer for Analog Circuits Using Integer Linear Programming Warm Started by Graph Drawing.	ICORES	2023	DBLP DOI BibTeX RDF
24	Rachel Selina Rajarathnam, Mohamed Baker Alawieh, Zixuan Jiang, Mahesh A. Iyer, David Z. Pan	DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit.	ASP-DAC	2022	DBLP DOI BibTeX RDF
24	Christos Georgakidis, Stavros Simoglou, Christos P. Sotiriou	RADPlace-MS: A Timing-Driven Placer and Optimiser for ASICs Radiation Hardening.	DFT	2022	DBLP DOI BibTeX RDF
24	Karim Malik, Colin Robertson, Douglas Braun, Clara Greig	U-Net convolutional neural network models for detecting and quantifying placer mining disturbances at watershed scales.	Int. J. Appl. Earth Obs. Geoinformation	2021	DBLP DOI BibTeX RDF
24	Jai-Ming Lin, Chung-Wei Huang, Liang-Chi Zane, Min-Chia Tsai, Che-Li Lin, Chen-Fa Tsai	Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs.	ICCAD	2021	DBLP DOI BibTeX RDF
24	Mohamed Ayman, Mahmoud Soliman	Robust pole-placer power system stabilisers design via complex Kharitonov's theorem.	Int. J. Model. Identif. Control.	2020	DBLP DOI BibTeX RDF
24	Frédéric Gessler, Philip Brisk, Mirjana Stojilovic	A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer.	VLSID	2020	DBLP DOI BibTeX RDF
24	Zhifeng Lin, Yanyue Xie, Gang Qian, Sifei Wang, Jun Yu 0010, Jianli Chen	Late Breaking Results: An Analytical Timing-Driven Placer for Heterogeneous FPGAs*.	DAC	2020	DBLP DOI BibTeX RDF
24	Prasun Datta, Shyamapada Mukherjee	Architecture-aware routability-driven placer for large-scale mixed-size designs.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
24	Nima Karimpour Darav, Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu	Multi-Commodity Flow-Based Spreading in a Commercial Analytic Placer.	FPGA	2019	DBLP DOI BibTeX RDF
24	Wuxi Li, Shounak Dhar, David Z. Pan	UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
24	Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen, Ismail Bustany	NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
24	Ziad Abuowaimer, Dani Maarouf, Timothy Martin, Jérémy Foxcroft, Gary Gréwal, Shawki Areibi, Anthony Vannelli	GPlace3.0: Routability-Driven Analytic Placer for UltraScale FPGA Architectures.	ACM Trans. Design Autom. Electr. Syst.	2018	DBLP DOI BibTeX RDF
24	Hisham M. Soliman, Ashraf Saleem, Tarek A. Tutunji, Serein Al Ratrout	Robust digital pole-placer for electric drives based on uncertain diophantine equation and interval mathematics.	Trans. Inst. Meas. Control	2018	DBLP DOI BibTeX RDF
24	Renaud De Landtsheer, Jean-Christophe Deprez, Christophe Ponsard	Optimal mapping of task-based computation models over heterogeneous hardware using placer.	MoDELS (Companion)	2018	DBLP DOI BibTeX RDF
24	Yu-Min Lee, Kuan-Te Pan, Chun Chen	NaPer: A TSV Noise-Aware Placer.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
24	Xu He, Yao Wang 0002, Yang Guo 0003, Sorin Cotofana	A Mixed-Size Monolithic 3D Placer with 2D Layout Inheritance.	ACM Great Lakes Symposium on VLSI	2017	DBLP DOI BibTeX RDF
24	Wan-Ning Wu, Chen Chen, Ching-Yu Chin, Chun-Kai Wang, Hung-Ming Chen	An analytical placer for heterogeneous FPGAs via rough-placed packing.	VLSI-DAT	2017	DBLP DOI BibTeX RDF
24	Wuxi Li, Shounak Dhar, David Z. Pan	UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packing.	ICCAD	2016	DBLP DOI BibTeX RDF
24	Tao Lin 0007, Chris C. N. Chu, Joseph R. Shinnerl, Ismail Bustany, Ivailo Nedelchev	POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2015	DBLP DOI BibTeX RDF
24	Endre Csóka, Attila Deák	A macro placer algorithm for chip design.	CoRR	2015	DBLP BibTeX RDF
24	Yu-Min Lee, Chun Chen, JiaXing Song, Kuan-Te Pan	A TSV noise-aware 3-D placer.	DATE	2015	DBLP BibTeX RDF
24	John Krumm, Dany Rouhana, Ming-Wei Chang	Placer++: Semantic place labels beyond the visit.	PerCom	2015	DBLP DOI BibTeX RDF
24	Yande Jiang, Xu He, Chang Liu 0019, Yang Guo 0003	An effective analytical 3D placer in monolithic 3D IC designs.	ASICON	2015	DBLP DOI BibTeX RDF
24	Sameer Pawanekar, Gaurav Trivedi	Net weighing based timing driven standard cell placer.	VDAT	2015	DBLP DOI BibTeX RDF
24	Ka-Ming Keung, Swamy D. Ponpandi, Akhilesh Tyagi	A placer for composable FPGA with 2D mesh network.	Int. J. Embed. Syst.	2014	DBLP DOI BibTeX RDF
24	Xin Yu, Xuanhua Shi, Hai Jin 0001, Xiaofei Liao, Song Wu 0001, Xiaoming Li	Page Classifier and Placer: A Scheme of Managing Hybrid Caches.	NPC	2014	DBLP DOI BibTeX RDF
24	Fubing Mao, Yi-Chung Chen, Wei Zhang 0012, Hai Li 0001	BMP: a fast B*-tree based modular placer for FPGAs (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF