Search results for "post-silicon"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
102	Subhasish Mitra, Sanjit A. Seshia, Nicola Nicolici	Post-silicon validation opportunities, challenges and recent advances.	DAC	2010	DBLP DOI BibTeX RDF	post-silicon validation
92	Amir Nahir, Avi Ziv, Rajesh Galivanche, Alan J. Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, Shakti Kapoor	Bridging pre-silicon verification and post-silicon validation.	DAC	2010	DBLP DOI BibTeX RDF	post-silicon, pre-silicon, verification, validation
92	Lin Xie, Azadeh Davoodi, Kewal K. Saluja	Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations.	DAC	2010	DBLP DOI BibTeX RDF	post-silicon diagnosis, process variations
86	Jagannath Keshava, Nagib Hakim, Chinna Prudvi	Post-silicon validation challenges: how EDA and academia can help.	DAC	2010	DBLP DOI BibTeX RDF	design, verification, test, validation, emulation
78	Yu Huang 0005, Wu-Tung Cheng	Using embedded infrastructure IP for SOC post-silicon verification.	DAC	2003	DBLP DOI BibTeX RDF	FPGA core, infrastructure IP (I-IP), post-silicon verification, transaction-based verification
75	Sung-Boem Park, Anne Bracy, Hong Wang 0003, Subhasish Mitra	BLoG: post-silicon bug localization in processors using bug localization graphs.	DAC	2010	DBLP DOI BibTeX RDF	IFRA, BLoG, silicon debug, post-silicon validation
75	Leonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng	A path-based methodology for post-silicon timing validation.	ICCAD	2004	DBLP DOI BibTeX RDF
74	Ilya Wagner, Valeria Bertacco	Reversi: Post-silicon validation system for modern microprocessors.	ICCD	2008	DBLP DOI BibTeX RDF
70	Sandip Ray, Warren A. Hunt Jr.	Connecting pre-silicon and post-silicon verification.	FMCAD	2009	DBLP DOI BibTeX RDF
59	Andrew DeOrio, Ilya Wagner, Valeria Bertacco	Dacota: Post-silicon validation of the memory subsystem in multi-core designs.	HPCA	2009	DBLP DOI BibTeX RDF
58	Charbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi	Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks.	ISQED	2009	DBLP DOI BibTeX RDF
58	Feng Wang 0004, Xiaoxia Wu, Yuan Xie 0001	Variability-driven module selection with joint design time optimization and post-silicon tuning.	ASP-DAC	2008	DBLP DOI BibTeX RDF
55	Lin Xie, Azadeh Davoodi	Representative path selection for post-silicon timing prediction under variability.	DAC	2010	DBLP DOI BibTeX RDF	process variations, post-silicon validation
55	Qunzeng Liu, Sachin S. Sapatnekar	Synthesizing a representative critical path for post-silicon delay prediction.	ISPD	2009	DBLP DOI BibTeX RDF	post-silicon optimization, representative critical path
55	Xiao Liu 0011, Qiang Xu 0001	Interconnection fabric design for tracing signals in post-silicon validation.	DAC	2009	DBLP DOI BibTeX RDF	trace-based debug, post-silicon validation
55	Vishal Khandelwal, Ankur Srivastava 0001	Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation.	ISPD	2007	DBLP DOI BibTeX RDF	post-silicon tunability, variability, stochastic optimization, timing optimization, gate sizing
49	Mahesh Ketkar, Eli Chiprout	A microarchitecture-based framework for pre- and post-silicon power delivery analysis.	MICRO	2009	DBLP DOI BibTeX RDF
49	Andrew DeOrio, Adam Bauserman, Valeria Bertacco	Post-silicon verification for cache coherence.	ICCD	2008	DBLP DOI BibTeX RDF
49	Shiyan Hu, Jiang Hu	Unified adaptivity optimization of clock and logic signals.	ICCAD	2007	DBLP DOI BibTeX RDF	clock signal tuning, logic signal tuning, post-silicon tuning, robustness, variation
47	Sarvesh H. Kulkarni, Dennis Sylvester, David T. Blaauw	Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
47	Farinaz Koushanfar, Petros Boufounos, Davood Shamsi	Post-silicon timing characterization by compressed sensing.	ICCAD	2008	DBLP DOI BibTeX RDF
47	Sung-Boem Park, Subhasish Mitra	IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors.	DAC	2008	DBLP DOI BibTeX RDF	verification, debug, validation, design for debug
47	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Automating post-silicon debugging and repair.	ICCAD	2007	DBLP DOI BibTeX RDF
47	Xin Li 0001, Brian Taylor, YuTsun Chien, Lawrence T. Pileggi	Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization.	ICCAD	2007	DBLP DOI BibTeX RDF
47	Sarvesh H. Kulkarni, Dennis Sylvester, David T. Blaauw	A statistical framework for post-silicon tuning through body bias clustering.	ICCAD	2006	DBLP DOI BibTeX RDF
45	John Goodenough 0001, Rob Aitken	Post-silicon is too late avoiding the $50 million paperweight starts with validated designs.	DAC	2010	DBLP DOI BibTeX RDF	low power design, emulation, post-silicon validation
45	Ho Fai Ko, Nicola Nicolici	Resource-Efficient Programmable Trigger Units for Post-Silicon Validation.	ETS	2009	DBLP DOI BibTeX RDF	programmable trigger unit, false trigger analysis, post-silicon validation
45	Kelageri Nagaraj, Sandip Kundu	Process variation mitigation via post silicon clock tuning.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	post-silicon tuning, performance, process variation
39	Ryan Cochran, Abdullah Nazma Nowroz, Sherief Reda	Post-silicon power characterization using thermal infrared emissions.	ISLPED	2010	DBLP DOI BibTeX RDF	power characterization, thermal infrared emissions
38	Rajeev K. Ranjan 0001, Claudionor Coelho, Sebastian Skalberg	Beyond verification: leveraging formal for debugging.	DAC	2009	DBLP DOI BibTeX RDF	behavioral indexing, post-silicon debugging, traceless debugging, formal verification, debugging, property verification
38	Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan	Online cache state dumping for processor debug.	DAC	2009	DBLP DOI BibTeX RDF	cache compression, processor debug, silicon debug, design for debug, post-silicon validation
37	Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton, Jin Yang 0006	BackSpace: Formal Analysis for Post-Silicon Debug.	FMCAD	2008	DBLP DOI BibTeX RDF
34	Pouria Bastani, Kip Killpack, Li-C. Wang, Eli Chiprout	Speedpath prediction based on learning from a small set of examples.	DAC	2008	DBLP DOI BibTeX RDF	speedpath, learning, timing analysis
34	Qing K. Zhu, Paige Kolze	Metal Fix and Power Network Repair for SOC.	ISVLSI	2006	DBLP DOI BibTeX RDF
33	Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita	Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging.	ICCD	2010	DBLP DOI BibTeX RDF
33	Qunzeng Liu, Sachin S. Sapatnekar	Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations.	DAC	2007	DBLP DOI BibTeX RDF
33	Li-C. Wang	Regression Simulation: Applying Path-Based Learning In Delay Test and Post-Silicon Validation.	DATE	2004	DBLP DOI BibTeX RDF
33	Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja	A yield improvement methodology using pre- and post-silicon statistical clock scheduling.	ICCAD	2004	DBLP DOI BibTeX RDF
32	Eli Chiprout	On-die power grids: the missing link.	DAC	2010	DBLP DOI BibTeX RDF	decap, voltage, locality, power grid, resonance
32	Saraju P. Mohanty	Unified Challenges in Nano-CMOS High-Level Synthesis.	VLSI Design	2009	DBLP DOI BibTeX RDF
32	Tommy Bojan, Igor Frumkin, Robert Mauri	Intel First Ever Converged Core Functional Validation Experience: Methodologies, Challenges, Results and Learning.	MTV	2007	DBLP DOI BibTeX RDF
31	Yousra Alkabani, Tammara Massey, Farinaz Koushanfar, Miodrag Potkonjak	Input vector control for post-silicon leakage current minimization in the presence of manufacturing variability.	DAC	2008	DBLP DOI BibTeX RDF	input vector control, low power, manufacturing variability
31	Zhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yuan Chao	Spare-cell-aware multilevel analytical placement.	DAC	2009	DBLP DOI BibTeX RDF	spare cells, placement, physical design
28	Subhasish Mitra	Robust System Design.	VLSI Design	2010	DBLP DOI BibTeX RDF	Robust systems, IFRA, BISER, Built-In Soft Error Resilience, Circuit Failure Prediction, On-line Self-Test, Reliability, Validation, aging, soft errors, post-silicon validation
28	Wenchao Li 0001, Alessandro Forin, Sanjit A. Seshia	Scalable specification mining for verification and diagnosis.	DAC	2010	DBLP DOI BibTeX RDF	error localization, verification, formal specification, debugging, diagnosis, assertions, post-silicon validation
28	Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih-Chieh Chang	An efficient phase detector connection structure for the skew synchronization system.	DAC	2010	DBLP DOI BibTeX RDF	adjustable delay buffer, phase detector, post-silicon tuning
28	Masahiro Fujita, Yoshihisa Kojima, Amir Masoud Gharehbaghi	Debugging from high level down to gate level.	DAC	2009	DBLP DOI BibTeX RDF	post-silicon debug, dependence analysis, system level design, equivalence checking, high-level design
28	Nicholas Callegari, Dragoljub Gagi Drmanac, Li-C. Wang, Magdy S. Abadir	Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch.	DAC	2010	DBLP DOI BibTeX RDF	data mining, learning, timing analysis, delay test
27	Ho Fai Ko, Nicola Nicolici	Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation.	DATE	2008	DBLP DOI BibTeX RDF
27	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Reap what you sow: spare cells for post-silicon metal fix.	ISPD	2008	DBLP DOI BibTeX RDF
27	Murari Mani, Ashish Kumar Singh, Michael Orshansky	Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization.	ICCAD	2006	DBLP DOI BibTeX RDF
27	Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak	Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies.	ITC	2003	DBLP DOI BibTeX RDF
26	Atanu Chattopadhyay, Zeljko Zilic	Serial reconfigurable mismatch-tolerant clock distribution.	DAC	2009	DBLP DOI BibTeX RDF	process variation, clock skew, clock networks
26	K. Uday Bhaskar, M. Prasanth, G. Chandramouli, V. Kamakoti 0001	A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip.	VLSI Design	2005	DBLP DOI BibTeX RDF
26	Anala, S. Gayathri, Ramesh Ramaswamy, Chetan Waghmare	An Approach to Mathematically Correlate Timing of Transaction Activity Between Pre-silicon and Post-silicon Environment.	SN Comput. Sci.	2020	DBLP DOI BibTeX RDF
26	Cheng Zhuo, Bei Yu 0001, Di Gao	Accelerating chip design with machine learning: From pre-silicon to post-silicon.	SoCC	2017	DBLP DOI BibTeX RDF
26	Eshan Singh, David Lin, Clark W. Barrett, Subhasish Mitra	Symbolic Quick Error Detection for Pre-Silicon and Post-Silicon Validation: Frequently Asked Questions.	IEEE Des. Test	2016	DBLP DOI BibTeX RDF
26	Fa Wang	Efficient Pre-Silicon Validation and Post-Silicon Tuning of Self-Healing Analog/RF Integrated Circuits.		2015	DOI RDF
26	Xin Li 0001, Fa Wang, Shupeng Sun, Chenjie Gu	Bayesian model fusion: a statistical framework for efficient pre-silicon validation and post-silicon tuning of complex analog and mixed-signal circuits.	ICCAD	2013	DBLP DOI BibTeX RDF
26	Prasanjeet Das, Sandeep K. Gupta 0001	Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning.	VTS	2013	DBLP DOI BibTeX RDF
26	Mehdi Dehbashi	Debug automation from pre-silicon to post-silicon.		2013	RDF
26	Mehdi Dehbashi, Görschwin Fey	Automated debugging from pre-silicon to post-silicon.	DDECS	2012	DBLP DOI BibTeX RDF
26	Allon Adir, Shady Copty, Shimon Landa, Amir Nahir, Gil Shurek, Avi Ziv, Charles Meissner, John Schumann	A unified methodology for pre-silicon verification and post-silicon validation.	DATE	2011	DBLP DOI BibTeX RDF
26	Allon Adir, Amir Nahir, Gil Shurek, Avi Ziv, Charles Meissner, John Schumann	Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor.	DAC	2011	DBLP DOI BibTeX RDF
26	Gary Miller, Bandana Bhattarai, Yu-Chin Hsu, Jay Dutt, Xi Chen 0024, George Bakewell	A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation.	DAC	2011	DBLP DOI BibTeX RDF
22	Robert C. Aitken	The challenges of correlating silicon and models in high variability CMOS processes.	ISPD	2009	DBLP DOI BibTeX RDF	design validation
22	Walid Ibrahim	A Novel EDA Tool for VLSI Test Vectors Management.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Test vectors selection, Genetic algorithms, Verification, VLSI, EDA tools
22	Ramyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham	A Scheme for On-Chip Timing Characterization.	VTS	2006	DBLP DOI BibTeX RDF
22	K. Uday Bhaskar, M. Prasanth, V. Kamakoti 0001, Kailasnath Maneparambil	A Framework for Automatic Assembly Program Generator (A2PG) for Verification and Testing of Processor Cores.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
21	Yongquan Fan, Zeljko Zilic	Accelerating jitter tolerance qualification for high speed serial interfaces.	ISQED	2009	DBLP DOI BibTeX RDF
21	Bonesi Stefano, Davide Bertozzi, Luca Benini, Enrico Macii	Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style.	DATE	2008	DBLP DOI BibTeX RDF
21	Desta Tadesse, D. Sheffield, E. Lenge, R. Iris Bahar, Joel Grodstein	Accurate timing analysis using SAT and pattern-dependent delay models.	DATE	2007	DBLP DOI BibTeX RDF
17	Fakir Sharif Hossain, Tomokazo Yuneda	An exquisitely sensitive variant-conscious post-silicon Hardware Trojan detection.	Integr.	2023	DBLP DOI BibTeX RDF
17	Gabriele Tombesi, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Maico Cassel dos Santos, Tianyu Jia, David Brooks 0001, Gu-Yeon Wei, Luca P. Carloni	SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs.	IEEE Des. Test	2023	DBLP DOI BibTeX RDF
17	Vedika Saravanan, Mohammad Walid Charrwi, Samah Mohamed Saeed	Revisiting Trojan Insertion Techniques for Post-Silicon Trojan Detection Evaluation.	ISVLSI	2023	DBLP DOI BibTeX RDF
17	Marco Gonzalez, David Bol	Post-Silicon Optimization of a Highly Programmable 64-MHz PLL Achieving 2.7-5.7 μW.	DATE	2023	DBLP DOI BibTeX RDF
17	Peter Domanski, Dirk Pflüger, Raphaël Latty	Learn to Tune: Robust Performance Tuning in Post-Silicon Validation.	ETS	2023	DBLP DOI BibTeX RDF
17	Kevin Weston, Vahid Janfaza, Abhishek Taur, Dhara Mungra, Arnav Kansal, Mohamed Zahran, Abdullah Muzahid	Post-Silicon Customization Using Deep Neural Networks.	ARCS	2023	DBLP DOI BibTeX RDF
17	Mohd Amiruddin Zainol, Sompon Khamron, Ng Gua Bin	Optimizing Post-Silicon Validation for FPGA Serial Configuration using an Automation Framework and Timing Characterization Verification.	ITC-Asia	2023	DBLP DOI BibTeX RDF
17	Judy Amanor-Badu, Ritchie Rice, Azizi Shuma, Rishik Bazaz, Horthense Tamdem	Pre and post silicon server platform transient performance using trans-inductor voltage regulator.	VTS	2023	DBLP DOI BibTeX RDF
17	Swati Shilaskar, Anup Behare, Ketki Sonawane, Shripad Bhatlawande	Post Silicon Validation for I2C (SMBUS) Peripheral.	VLSID	2023	DBLP DOI BibTeX RDF
17	Masoud Pashaeifar, Leo C. N. de Vreede, Morteza S. Alavi	A Millimeter-Wave CMOS Series-Doherty Power Amplifier With Post-Silicon Inter-Stage Passive Validation.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
17	Yiannakis Sazeides, Arkady Bramnik, Ron Gabor, Ramon Canal	A Real-Time Error Detection (RTD) Architecture and Its Use for Reliability and Post-Silicon Validation for F/F Based Memory Arrays.	IEEE Trans. Emerg. Top. Comput.	2022	DBLP DOI BibTeX RDF
17	Sheriff Sadiqbatcha, Jinwei Zhang, Hussam Amrouch, Sheldon X.-D. Tan	Real-Time Full-Chip Thermal Tracking: A Post-Silicon, Machine Learning Perspective.	IEEE Trans. Computers	2022	DBLP DOI BibTeX RDF
17	Yiwen Liao, Bin Yang 0009, Raphaël Latty, Jochen Rivoir	A Deep-Learning-Aided Pipeline for Efficient Post-Silicon Tuning.	CoRR	2022	DBLP DOI BibTeX RDF
17	Yiwen Liao, Raphaël Latty, Bin Yang 0009	Experts in the Loop: Conditional Variable Selection for Accelerating Post-Silicon Analysis Based on Deep Learning.	CoRR	2022	DBLP DOI BibTeX RDF
17	Yi Lv, Houpeng Chen, Qian Wang, Xi Li 0012, Chenchen Xie, Zhitang Song	Post-silicon nano-electronic device and its application in brain-inspired chips.	Frontiers Neurorobotics	2022	DBLP DOI BibTeX RDF
17	Sih Pin Tan, Yung It Ho	Scalability of Post-Silicon Test Generation for Multi-core RISC-V SOC Validation.	MCSoC	2022	DBLP DOI BibTeX RDF
17	Hussam Amrouch, Krishnendu Chakrabarty, Dirk Pflüger, Ilia Polian, Matthias Sauer 0002, Matteo Sonza Reorda	Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization.	ETS	2022	DBLP DOI BibTeX RDF
17	Qiang Fang, Longyang Lin, Yao Zu Wong, Hui Zhang, Massimo Alioto	Side-Channel Attack Counteraction via Machine Learning-Targeted Power Compensation for Post-Silicon HW Security Patching.	ISSCC	2022	DBLP DOI BibTeX RDF
17	Riccardo Cantoro, Francesco Garau, Riccardo Masante, Sandro Sartoni, Virendra Singh, Matteo Sonza Reorda	Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries.	VTS	2022	DBLP DOI BibTeX RDF
17	Jun-Yang Lei, Abhijit Chatterjee	ML-Assisted Bug Emulation Experiments for Post-Silicon Multi-Debug of AMS Circuits.	ITC	2022	DBLP DOI BibTeX RDF
17	Sidhartha Sankar Rout, Sujay Deb, Kanad Basu	WiND: An Efficient Post-Silicon Debug Strategy for Network on Chip.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2021	DBLP DOI BibTeX RDF
17	Sheriff Sadiqbatcha, Jinwei Zhang, Hengyang Zhao, Hussam Amrouch, Jörg Henkel, Sheldon X.-D. Tan	Post-Silicon Heat-Source Identification and Machine-Learning-Based Thermal Modeling Using Infrared Thermal Imaging.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2021	DBLP DOI BibTeX RDF
17	Debjit Pal, Shobha Vasudevan	Feature Engineering for Scalable Application-Level Post-Silicon Debugging.	CoRR	2021	DBLP BibTeX RDF
17	Peter Domanski, Dirk Pflüger, Jochen Rivoir, Raphaël Latty	Self-Learning Tuning for Post-Silicon Validation.	CoRR	2021	DBLP BibTeX RDF
17	Pantea Kiaei, Zhenyuan Liu, Ramazan Kaan Eren, Yuan Yao, Patrick Schaumont	Saidoyoki: Evaluating side-channel leakage in pre- and post-silicon setting.	IACR Cryptol. ePrint Arch.	2021	DBLP BibTeX RDF
17	Subashree Raja, Padmaja Bhamidipati, Xiaobang Liu, Ranga Vemuri	Security Capsules: An Architecture for Post-Silicon Security Assertion Validation for Systems-on-Chip.	ISVLSI	2021	DBLP DOI BibTeX RDF
17	Tom Kolan, Hillel Mendelson, Vitali Sokhin, Shai Doron, Hernan Theiler, Shay Aviv, Hagai Hadad, Natalia Freidman, Elena Tsanko, John M. Ludden, Bryant Cockcroft	Post Silicon Validation of the MMU.	DATE	2021	DBLP DOI BibTeX RDF
17	Sandip Ray, Arani Sinha	Synergies Between Delay Test and Post-silicon Speed Path Validation: A Tutorial Introduction.	ETS	2021	DBLP DOI BibTeX RDF