Search results for "rail"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
118	Saed G. Younis, Thomas F. Knight Jr.	Non-dissipative rail drivers for adiabatic circuits.	ARVLSI	1995	DBLP DOI BibTeX RDF	driver circuits, distributed parameter networks, lumped parameter networks, passive networks, nondissipative rail drivers, adiabatic circuits, CMOS charge recovery logic, energy dissipation per operation, SCRL circuits, rail waveform generation, rail driver circuit, multiple harmonics, harmonic rail driver, passive reactive components, trimmed transmission line segments, CMOS logic circuits, CMOS circuits, harmonics
116	Nebojsa J. Bojovic, Milos Milenkovic	The best rail fleet mix problem.	Oper. Res.	2008	DBLP DOI BibTeX RDF	Rail freight car, Multiple criteria decision aiding, AHP method
109	Kazuteru Namba, Hideo Ito	Delay Fault Testability on Two-Rail Logic Circuits.	DFT	2008	DBLP DOI BibTeX RDF
97	John R. Wilson, Beverley J. Norris	Human factors in support of a successful railway: a review.	Cogn. Technol. Work.	2006	DBLP DOI BibTeX RDF	Centres, Trains, Human factors, Safety, Signalling, Railways
96	Hwang-Cherng Chow, Pu-Nan Weng	A Low Voltage Rail-to-Rail OPAMP Design for Biomedical Signal Filtering Applications.	DELTA	2008	DBLP DOI BibTeX RDF	rail-to-rail, current driven bulk, filter, low voltage, biomedical signal
91	Vijay Rentala, Saroj Rout, Edward Lee, Robert J. Weber	A constant GM rail-to-rail opamp with a novel input stage for BiCMOS process.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
87	Danil Sokolov, Julian P. Murphy, Alexandre V. Bystrov, Alexandre Yakovlev	Design and Analysis of Dual-Rail Circuits for Security Applications.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Alternating spacer protocol, dual-rail encoding, hazard-free design, cryptography, power analysis, design automation, hardware security
87	Clelia Mandriota, Massimiliano Nitti, Nicola Ancona, Ettore Stella, Arcangelo Distante	Filter-based feature selection for rail defect detection.	Mach. Vis. Appl.	2004	DBLP DOI BibTeX RDF	Rail detection, Texture feature, Filter bank, K-nearest neighbor classifier
87	Dimitris Nikolos	Self-Testing Embedded Two-Rail Checkers.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	parity tree, embedded self-testing, self testing, two-rail checker, parity checker
81	Antonio J. López-Martín, Alfonso Carlosena, Jaime Ramírez-Angulo, Ramón González Carvajal	Rail-to-rail tunable CMOS V-I converter.	ISCAS	2006	DBLP DOI BibTeX RDF
81	Juan M. Carrillo, J. Francisco Duque-Carrillo, Antonio Jesús Torralba Silgado, Ramón González Carvajal	Class-AB rail-to-rail CMOS analog buffer.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
81	S. V. Gopalaiah, A. P. Shivaprasad, Sukanta K. Panigrahi	Design of Low Voltage Low Power CMOS OP-AMPS with Rail-to-Rail Input/Output Swing.	VLSI Design	2004	DBLP DOI BibTeX RDF
81	Takahide Sato, Shigetaka Takagi, Nobuo Fujii	Rail-to-rail OTA using a pair of single channel type MOSFETs.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
76	Feng Zhang 0014, Zongren Yang, Wei Feng, Hao Cui, Lingyi Huang, Weiwu Hu	A High Speed CMOS Transmitter and Rail-to-Rail Receiver.	DELTA	2008	DBLP DOI BibTeX RDF	LVDS rail-to-rail
76	Filipe Costa Beber Vieira, César Augusto Prior, Cesar Ramos Rodrigues, Leonardo Perin, João Baptista dos Santos Martins	Current mode instrumentation amplifier with rail-to-rail input and output.	SBCCI	2007	DBLP DOI BibTeX RDF	current mode instrumentation amplifier, rail-to-rail input and output, analog integrated circuits
76	Hui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu	A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach.	ISLPED	2004	DBLP DOI BibTeX RDF	CMOS analog circuit, flash analog-to-digital converter, rail-to-rail, low power, comparator
76	Mohammad M. Ahmadi, Reza Lotfi	A new architecture for rail-to-rail input constant-gm CMOS operational transconductance amplifiers.	ISLPED	2003	DBLP DOI BibTeX RDF	current summation, floating current source, input stage, rail-to-rail, transconductance, operational transconductance amplifier
74	Karthik Baddam, Mark Zwolinski	Divided Backend Duplication Methodology for Balanced Dual Rail Routing.	CHES	2008	DBLP DOI BibTeX RDF	Dual Rail Routing, Dual Rail FPGA Implementation, Differential Power Analysis
74	Cecilia Metra, Michele Favalli, Bruno Riccò	Embedded two-rail checkers with on-line testing ability.	VTS	1996	DBLP DOI BibTeX RDF	embedded two-rail checkers, online testing ability, self-testing ability, compact structure, VLSI, logic testing, integrated circuit testing, design for testability, error detection, automatic testing, integrated logic circuits, two-rail code
74	Kees van Berkel 0001, Ronan Burgess, Joep L. W. Kessels, Ad M. G. Peeters, Marly Roncken, Frits D. Schalij, Rik van de Wiel	A single-rail re-implementation of a DCC error detector using a generic standard-cell library.	ASYNC	1995	DBLP DOI BibTeX RDF	digital audio tape, DCC error detector, generic standard-cell library, single-rail re-implementation, fully asynchronous implementation, handshake signaling, single-rail data encoding, generic cell library, high-level Tangram description, intermediate architecture, high level synthesis, asynchronous circuits, error detection codes, integrated logic circuits, cellular arrays, power dissipation, handshake circuits
70	Bin Ning, Tao Tang 0004, Ziyou Gao, Fei Yan, Fei-Yue Wang 0001, Daniel Zeng 0001	Intelligent Railway Systems in China.	IEEE Intell. Syst.	2006	DBLP DOI BibTeX RDF	rail transportation, intelligent rail transportation systems, Chinese rail transportation network
70	Elisangela Mieko Kanacilo, Alexander Verbraeck	A distributed multi-formalism simulation to support rail infrastructure control design.	WSC	2005	DBLP DOI BibTeX RDF
70	Danil Sokolov, Julian P. Murphy, Alexandre V. Bystrov, Alexandre Yakovlev	Improving the Security of Dual-Rail Circuits.	CHES	2004	DBLP DOI BibTeX RDF
62	Edward K. F. Lee, Anthony Lam, Taihu Li	A 0.65V rail-to-rail constant gm opamp for biomedical applications.	ISCAS	2008	DBLP DOI BibTeX RDF
62	Fuding Ge, Malay Trivedi, Brent Thomas, William Jiang, Hongjiang Song	1.5V 0.5mW 2MSPS 10B DAC with rail-to-rail output in 0.13mum CMOS technology.	SoCC	2008	DBLP DOI BibTeX RDF
62	Jaime Ramírez-Angulo, Lalitha Mohana Kalyani-Garimella, Annajirao Garimella, Sri Raga Sudha Garimella, Antonio J. López-Martín, Ramón González Carvajal	An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators.	VLSI Design	2008	DBLP DOI BibTeX RDF
62	Edward K. Lee 0002, Eusebiu Matei, Ravi S. Ananth	A 0.9 V rail-to-rail constant gm amplifier for implantable biomedical applications.	ISCAS	2006	DBLP DOI BibTeX RDF
62	Shouli Yan, Jingyu Hu, Tongyu Song, Edgar Sánchez-Sinencio	A constant-gm rail-to-rail op amp input stage using dynamic current scaling technique.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
62	Pablo Aguirre, Fernando Silveira	Design of a Reusable Rail-to-Rail Operational Amplifier.	SBCCI	2003	DBLP DOI BibTeX RDF
62	Chih-Wen Lu	A new rail-to-rail driving scheme and a low-power high-speed output buffer amplifier for AMLCD column driver application.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
62	Dingtzay Chen, Hongchin Lin	An 1 V rail-rail low-power CMOS op-amp.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
62	Christian Jesús B. Fayomi, Gordon W. Roberts, Mohamad Sawan	A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18 um CMOS technology.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
62	Daniele Gardino, Franco Maloberti	High resolution rail-to-rail ADC in CMOS digital technology.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
60	Abhinav Vishnu, Gopalakrishnan Santhanaraman, Wei Huang 0003, Hyun-Wook Jin, Dhabaleswar K. Panda 0001	Supporting MPI-2 One Sided Communication on Multi-rail InfiniBand Clusters: Design Challenges and Performance Benefits.	HiPC	2005	DBLP DOI BibTeX RDF
58	Jeong-Hun Shin, JaeSub Kim, Keuntae Park, Daeyeon Park	Railroad: virtual infrastructure for data dissemination in wireless sensor networks.	PE-WASUN	2005	DBLP DOI BibTeX RDF	wireless sensor networks, energy efficiency, data dissemination, hot spot, mobility support
58	Märt Saarepera, Tomohiro Yoneda	A Self-Timed Implementation of Boolean Functions.	ASYNC	1999	DBLP DOI BibTeX RDF
58	Lauren J. Thomas, Daniel J. A. Rhind, Katie J. Robinson	Rail passenger perceptions of risk and safety and priorities for improvement.	Cogn. Technol. Work.	2006	DBLP DOI BibTeX RDF	Rail passenger, Safety preferences, Risk perception
58	Himanshu Joshi, Subhrajit Guhathakurta, Goran Konjevod, John Crittenden, Ke Li	Simulating impact of light rail on urban growth in Phoenix: an application of urbansim modeling environment.	DG.O	2006	DBLP DOI BibTeX RDF	light rail, ridership, simulation, transit, urban modeling
58	Zhimin Chen, Yujie Zhou	Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage.	CHES	2006	DBLP DOI BibTeX RDF	Gate Level Masking, DRSL, Dual-Rail, Pre-charge, Side Channel Attacks, DPA
58	Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra	Low Cost and High Speed Embedded Two-Rail Code Checker.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Self-checking circuits, checkers, error indicators, two-rail code
58	Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama	Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic.	PRDC	2000	DBLP DOI BibTeX RDF	dual-rail differential logic, multiple-valued current-mode circuits, asynchronous-control circuit, logic testing, asynchronous circuits, self-checking circuit, current-mode logic, current-mode circuits
58	Ad M. G. Peeters, Kees van Berkel 0001	Single-rail handshake circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	single-rail handshake circuits, four-phase handshake protocol, standard-cell library, technology migration, low-power applications, VLSI, protocols, energy-efficient, asynchronous circuits, asynchronous circuits, integrated logic circuits, cellular arrays
55	Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama	Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic.	ISMVL	1995	DBLP DOI BibTeX RDF	multiple-valued arithmetic integrated circuits, dual-rail source-coupled logic, multiple-valued current-mode MOS integrated circuit, high-speed arithmetic systems, multiple-valued source-coupled logic circuit, dual-rail complementary inputs, pipelined multiplier, 54 bit, 200 MHz, 0.8 mum, 1.5 V, CMOS logic circuits, multiplying circuits, multivalued logic circuits, current-mode logic, pipeline arithmetic
50	Donghun Lee 0002, Sungcheul Lee, Namkuk Ku, Chaemook Lim, Kyu-Yeul Lee, Tae-wan Kim 0001, JongWon Kim 0002	Development and application of a novel rail runner mechanism for double hull structures of ships.	ICRA	2008	DBLP DOI BibTeX RDF
50	Colin Murray Eustace	Simulation of Queensland coal rail operations.	WSC	2008	DBLP DOI BibTeX RDF
50	Andrea Balluchi, Antonio Bicchi, Emanuele Mazzi, Alberto L. Sangiovanni-Vincentelli, Gabriele Serra	Hybrid Modelling and Control of the Common Rail Injection System.	HSCC	2006	DBLP DOI BibTeX RDF
50	Byung Kwon Lee, Bong Joo Jung, Kap Hwan Kim, Soon Oh Park, Jeong Hoon Seo	A simulation study for designing a rail terminal in a container port.	WSC	2006	DBLP DOI BibTeX RDF
50	Akira Mochizuki, Takahiro Hanyu	Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic.	ISMVL	2006	DBLP DOI BibTeX RDF
50	Quan Lu, Maged M. Dessouky, Robert C. Leachman	Modeling train movements through complex rail networks.	ACM Trans. Model. Comput. Simul.	2004	DBLP DOI BibTeX RDF	modeling, Trains, deadlock, dispatching
50	Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra	High Speed and Highly Testable Parallel Two-Rail Code Checker.	DATE	2003	DBLP DOI BibTeX RDF
50	Maged M. Dessouky, Quan Lu, Robert C. Leachman	Modeling very large scale systems: using simulation modeling to assess rail track infrastructure in densely trafficked metropolitan areas.	WSC	2002	DBLP DOI BibTeX RDF
50	Clelia Mandriota, Ettore Stella, Massimiliano Nitti, Nicola Ancona, Arcangelo Distante	Rail corrugation detection by Gabor filtering.	ICIP (2)	2001	DBLP DOI BibTeX RDF
50	Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama	Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic.	ISMVL	1999	DBLP DOI BibTeX RDF
48	Takahiro Hanyu, Tomohiro Takahashi, Michitaka Kameyama	Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic.	ISMVL	2003	DBLP DOI BibTeX RDF
48	David W. Lloyd, Jim D. Garside	A Practical Comparison of Asynchronous Design Styles.	ASYNC	2001	DBLP DOI BibTeX RDF
48	Antonis M. Paschalis, Dimitris Gizopoulos, Nikolaos Gaitanis	Concurrent Delay Testing in Totally Self-Checking Systems.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	concurrent on-line detection, duplication systems, path delay faults, totally self-checking circuits, error indicators
48	Sarah Sharples, Nora Balfe, David Golightly, Laura Millen	Understanding the Impact of Rail Automation.	HCI (17)	2009	DBLP DOI BibTeX RDF	rail, simulation, performance, automation, observation, workload
48	Ying Qian, Ahmad Afsahi	Efficient shared memory and RDMA based collectives on multi-rail QsNetII SMP clusters.	Clust. Comput.	2008	DBLP DOI BibTeX RDF	Multi-rail networks, Clusters, Shared-memory, Collective communications, SMP, RDMA
48	Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti	Three-Phase Dual-Rail Pre-charge Logic.	CHES	2006	DBLP DOI BibTeX RDF	dual-rail logic, SABL, security, DPA
48	Thomas Popp, Stefan Mangard	Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints.	CHES	2005	DBLP DOI BibTeX RDF	Hardware Countermeasures, MDPL, Masking Logic, Dual-Rail Pre-Charge Logic, DPA, Side-Channel Analysis
48	Stanislaw J. Piestrak	Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	embedded circuit, inverter-free circuit, totally self-testing circuit, concurrent error detection, Berger code, self-testing checker, two-rail code
48	Michele Favalli, Cecilia Metra	Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	bus based systems, on-line testing, two-rail checker
46	Anjali Gopinath, Ravi Kumar Adusumalli, Veeresh Babu Vulligaddala, M. B. Srinivas	A Switched-Capacitor Amplifier with True Rail-to-Rail Input Range without Using a Rail-to-Rail Op-Amp.	VLSID	2017	DBLP DOI BibTeX RDF
46	J. H. Botma, R. F. Wassenaar, Remco J. Wiegerink	A Low-voltage CMOS Op Amp with a Rail-to-rail Constant-gm Input Stage and a Class AB Rail-to-rail Output Stage.	ISCAS	1993	DBLP BibTeX RDF
43	Weixun Yan, Robert Kolm, Horst Zimmermann	A low-voltage low-power fully differential rail-to-rail input/output opamp in 65-nm CMOS.	ISCAS	2008	DBLP DOI BibTeX RDF
43	Zhenyu Yang, Zhangwen Tang, Hao Min	A fully differential charge pump with accurate current matching and rail-to-rail common-mode feedback circuit.	ISCAS	2008	DBLP DOI BibTeX RDF
43	Trung-Kien Nguyen, Sang-Gug Lee 0001	Low-voltage, low-power CMOS operation transconductance amplifier with rail-to-rail differential input range.	ISCAS	2006	DBLP DOI BibTeX RDF
43	Hong-Yi Huang, Bo-Ruei Wang, Jen-Chieh Liu	High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit.	ISCAS	2006	DBLP DOI BibTeX RDF
43	H. Dine, S. Chuang, Phillip E. Allen, Paul E. Hasler	A rail to rail, slew-boosted pre-charge buffer.	ISCAS	2006	DBLP DOI BibTeX RDF
43	Chih-Wen Lu, Peter H. Xiao	A High-Speed Low-Power Rail-to-Rail Buffer Amplifier for LCD Application.	CCECE	2006	DBLP DOI BibTeX RDF
43	Holly Pekau, Lee Hartley, James W. Haslett	A re-configurable high-speed CMOS track and latch comparator with rail-to-rail input for IF digitization [software radio receiver applications].	ISCAS (6)	2005	DBLP DOI BibTeX RDF
43	Shouli Yan, Jingyu Hu, Tongyu Song	Novel and robust constant-gm technique for rail-to-rail CMOS amplifier input stages.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
43	Takeshi Yoshida, Miho Akagi, Mamoru Sasaki, Atsushi Iwata	A 1V supply successive approximation ADC with rail-to-rail input voltage range.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
43	Chun-Jen Huang, Hong-Yi Huang	A low-voltage CMOS rail-to-rail operational amplifier using double p-channel differential input pairs.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
43	Rahul Shukla, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal	A low voltage rail to rail V-I conversion scheme for applications in current mode A/D converters.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
43	S. V. Gopalaiah, A. P. Shivaprasad	Low Voltage CMOS op-amp with Rail-to-Rail Input/Output Swing.	DELTA	2004	DBLP DOI BibTeX RDF
43	Srinjoy Mitra, A. N. Chandorkar	Design of Amplifier with Rail-to-Rail CMR with 1V Power Supply.	VLSI Design	2004	DBLP DOI BibTeX RDF
43	Juan M. Carrillo, J. Francisco Duque-Carrillo, Guido Torelli, José L. Ausín	1-V quasi constant-gm input/output rail-to-rail CMOS op-amp.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
43	Juan M. Carrillo, J. Francisco Duque-Carrillo, Guido Torelli, José L. Ausín	Constant-gm constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
43	V. Kasemsuwan, P. Boonyaporn, Apinunt Thanachayanont	±1.5V high performance CMOS rail to rail voltage follower.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
43	Christian Jesús B. Fayomi, Mohamad Sawan, Gordon W. Roberts	A design strategy for a 1-V rail-to-rail input/output CMOS opamp.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
43	Soliman A. Mahmoud, Ahmed M. Soliman	The current-feedback differential difference amplifier: new CMOS realization with rail to rail class-AB output stage.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
43	Mohamed Dessouky, Andreas Kaiser	Rail-to-rail operation of very low voltage CMOS switched-capacitor circuits.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
43	Gensoh Matsubara, Nobuhiro Ide	A Low Power Zero-Overhead Self-Timed Division and Square Root Unit Combining a Single-Rail Static Circuit with a Dual-Rail Dynamic Circuit.	ASYNC	1997	DBLP DOI BibTeX RDF	floating point, division, square root, self-timed
42	Ali Vaezi, Manish Verma	An analytics approach to dis-aggregate national freight data to estimate hazmat traffic on rail-links and at rail-yards in Canada.	J. Rail Transp. Plan. Manag.	2017	DBLP DOI BibTeX RDF
42	Ahmadreza Talebian, Bo Zou	A multi-stage approach to air-rail competition: Focus on rail agency objective, train technology and station access.	J. Rail Transp. Plan. Manag.	2016	DBLP DOI BibTeX RDF
41	Eric Menendez, Ken Mai	A High-Performance, Low-Overhead, Power-Analysis-Resistant, Single-Rail Logic Style.	HOST	2008	DBLP DOI BibTeX RDF
41	Jian-hua Qiao, Lin-sheng Li, Jinggang Zhang	Design of Rail Surface Crack-detecting System Based on Linear CCD Sensor.	ICNSC	2008	DBLP DOI BibTeX RDF
41	Kazuteru Namba, Hideo Ito	Path Delay Fault Test Set for Two-Rail Logic Circuits.	PRDC	2008	DBLP DOI BibTeX RDF
41	Alin Razafindraibe, Michel Robert, Philippe Maurine	Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA.	PATMOS	2007	DBLP DOI BibTeX RDF
41	Alin Razafindraibe, Michel Robert, Philippe Maurine	Improvement of dual rail logic as a countermeasure against DPA.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
41	Ying Qian, Ahmad Afsahi	High Performance RDMA-based Multi-port All-gather on Multi-rail QsNet II.	HPCS	2007	DBLP DOI BibTeX RDF
41	Thomas F. Brady	Modeling the Indiana coal rail transportation infrastructure.	WSC	2007	DBLP DOI BibTeX RDF
41	Frédéric Maire	Vision based anti-collision system for rail track maintenance vehicles.	AVSS	2007	DBLP DOI BibTeX RDF
41	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Current Mode On-Chip Interconnect using Level-Encoded Two-Phase Dual-Rail Encoding.	ISCAS	2007	DBLP DOI BibTeX RDF
41	Elisangela Mieko Kanacilo, Alexander Verbraeck	Simulation services to support the control design of rail infrastructures.	WSC	2006	DBLP DOI BibTeX RDF
41	Ying Qian, Ahmad Afsahi	Efficient RDMA-based multi-port collectives on multi-rail QsNetII clusters.	IPDPS	2006	DBLP DOI BibTeX RDF
41	Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine	A Method to Design Compact Dual-rail Asynchronous Primitives.	PATMOS	2005	DBLP DOI BibTeX RDF
41	Bruno Cabral, Paulo Marques, Luís Moura Silva	RAIL: code instrumentation for .NET.	SAC	2005	DBLP DOI BibTeX RDF	NET platform, runtime, code instrumentation
41	Geun Rae Cho, Tom Chen 0001	Synthesis of single/dual-rail mixed PTL/static logic for low-power applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF