Search results for "scan-chain"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
154	Yu Huang 0005, Ruifeng Guo, Wu-Tung Cheng, James Chien-Mo Li	Survey of Scan Chain Diagnosis.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
116	Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee	Functional Scan Chain Testing.	DATE	1998	DBLP DOI BibTeX RDF	functional scan chain, alternating sequence, scan chain testing, design for testability, test point insertion
106	Xiaoxia Wu, Paul Falkenstern, Krishnendu Chakrabarty, Yuan Xie 0001	Scan-chain design and optimization for three-dimensional integrated circuits.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	scan-chain design, genetic algorithm, integer linear programming, randomized rounding, LP relaxation, 3D ICs
104	Kwang-Ting Cheng	Partial scan designs without using a separate scan clock.	VTS	1995	DBLP DOI BibTeX RDF	flip-flop selection method, flip-flop test generation method, scan registers ordering, scan-shifting concept, test vector compaction, delay fault detection, cycle breaking, logic testing, delays, timing, design for testability, logic design, automatic testing, DFT, fault coverage, flip-flops, circuit optimisation, boundary scan testing, scan chain, combinatorial optimization problem, test generation algorithm, partial scan designs, system clock
103	Wei Li 0023, Seongmoon Wang, Srimat T. Chakradhar, Sudhakar M. Reddy	Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage.	VLSI Design	2005	DBLP DOI BibTeX RDF
101	Abhijit Jas, Bahram Pouya, Nur A. Touba	Test data compression technique for embedded cores using virtual scan chains.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
99	Nilabha Dev, Sandeep Bhatia, Subhasish Mukherjee, Sue Genova, Vinayak Kadam	A Partitioning Based Physical Scan Chain Allocation Algorithm that Minimizes Voltage Domain Crossings.	VLSI Design	2008	DBLP DOI BibTeX RDF
98	Xiaoxia Wu, Paul Falkenstern, Yuan Xie 0001	Scan chain design for three-dimensional integrated circuits (3D ICs).	ICCD	2007	DBLP DOI BibTeX RDF
97	Geewhun Seok, Il-soo Lee, Tony Ambler, Baxter F. Womack	An Efficient Scan Chain Partitioning Scheme with Reduction of Test Data under Routing Constraint.	DFT	2006	DBLP DOI BibTeX RDF
95	Ozgur Sinanoglu, Alex Orailoglu	Modeling Scan Chain Modifications For Scan-in Test Power Minimization.	ITC	2003	DBLP DOI BibTeX RDF
94	Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen	Peak-power reduction for multiple-scan circuits during test application.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	peak-power reduction, multiple scan chain based circuits, peak periodicity, peak width, power waveforms, scan-based circuits, delay buffers, interleaving scan technique, data output, logic testing, logic testing, delays, integrated circuit testing, application specific integrated circuits, SOC, boundary scan testing
94	Abhijit Jas, Bahram Pouya, Nur A. Touba	Virtual Scan Chains: A Means for Reducing Scan Length in Cores.	VTS	2000	DBLP DOI BibTeX RDF	Compression/Decompression, Virtual Scan, Built-In Self-Test, Mapping, Design-for-Testability, LFSR, System Integrator, Integrated Circuits, Integrated Circuits, Scan Chains, Embedded Cores, Digital Testing, Reseeding
93	Sunghoon Chun, Taejin Kim, YongJoon Kim, Sungho Kang 0001	An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation.	VTS	2008	DBLP DOI BibTeX RDF	Scan chain based test, Diagnosis, Symbolic Simulation
90	Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara	Improving test effectiveness of scan-based BIST by scan chain partitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
81	Sying-Jyan Wang, Kuo-Lin Peng, Kuang-Cyun Hsiao, Katherine Shu-Min Li	Layout-aware scan chain reorder for launch-off-shift transition test coverage.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	scan chain ordering, test generation, transition faults, Scan test
80	Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara	Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
79	Robert B. Norwood, Edward J. McCluskey	Synthesis-for-scan and scan chain ordering.	VTS	1996	DBLP DOI BibTeX RDF	synthesis-for-scan procedure, scan chain ordering, testable circuit design, beneficial scan, VLSI, logic testing, integrated circuit testing, design for testability, logic design, sequential circuits, logic synthesis, flip-flops, integrated circuit design, integrated logic circuits, test strategy, boundary scan testing, functional specifications
79	Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen	Cost-free scan: a low-overhead scan path design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
79	Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
76	Swaroop Ghosh, K. W. Lai, Wen-Ben Jone, Shih-Chieh Chang	Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
75	Kuen-Jong Lee, Tsung-Chu Huang	An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	multiple scan chains, interleaving scan, test power reduction, peak power reduction
75	Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen	Cost-free scan: a low-overhead scan path design methodology.	ICCAD	1995	DBLP DOI BibTeX RDF	Testing, DFT, Scan design
73	Fei Wang, Yu Hu 0001, Huawei Li 0001, Xiaowei Li 0001	A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults.	ASP-DAC	2008	DBLP DOI BibTeX RDF
73	Hideo Fujiwara, Akihiro Yamamoto	Parity-scan design to reduce the cost of test application.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
72	Puneet Gupta 0001, Andrew B. Kahng, Stefanus Mantik	Routing-aware scan chain ordering.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	testing, Layout, scan chain
72	Irith Pomeranz	Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
71	Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy 0001	Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST.	DFT	2003	DBLP DOI BibTeX RDF
70	Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy	On reducing test application time for scan circuits using limited scan operations and transfer sequences.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
70	Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita	Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	scan tree, logic testing, design for testability, sequential circuit
70	Dong Xiang, Kaiwei Li, Hideo Fujiwara	Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
70	Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita	Reducing Scan Shifts Using Folding Scan Trees.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
69	Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu	Scan Power Reduction Through Test Data Transition Frequency Analysis.	ITC	2002	DBLP DOI BibTeX RDF
69	Yu Huang 0005, Wu-Tung Cheng, Greg Crowell	Using fault model relaxation to diagnose real scan chain defects.	ASP-DAC	2005	DBLP DOI BibTeX RDF
68	Puneet Gupta 0001, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma	Layout-aware scan chain synthesis for improved path delay fault coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
67	Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang	A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	profiling, design for testability, Diagnosis, fault, scan chain
67	Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu	Reducing Average and Peak Test Power Through Scan Chain Modification.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	test power reduction, scan chain modification, average test power, peak test power, scan testing
67	Yuejian Wu	Diagnosis of Scan Chain Failures.	DFT	1998	DBLP DOI BibTeX RDF	scan chain designs, fault diagnosis, design for testability
67	Wei-Lun Wang, Kuen-Jong Lee	An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	mixed-mode pattern generation, built-in self-test, power consumption, test application time, scan chain
66	Nan-Cheng Lai, Sying-Jyan Wang, Y.-H. Fu	Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
66	Yu Huang 0005, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung	Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis.	DATE	2004	DBLP DOI BibTeX RDF
65	Irith Pomeranz, Sudhakar M. Reddy	On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains.	ICCD	2002	DBLP DOI BibTeX RDF
62	Junichi Hirase, Naoki Shindou, Kouji Akahori	Scan Chain Diagnosis Using IDDQ Current Measurement.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
62	Ozgur Sinanoglu	Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Test power reduction, Scan power reduction, Serial transformations, Scan chain modification, Design for testability, Core-based testing
60	Ozgur Sinanoglu, Alex Orailoglu	Aggressive Test Power Reduction Through Test Stimuli Transformation.	ICCD	2003	DBLP DOI BibTeX RDF
60	Dong Xiang, Mingjing Chen, Hideo Fujiwara	Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Random testability, scan enable signal, weighted random testing, scan-based BIST
60	Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara	Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Scan forest, test application cost, test data volume, test power
60	Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang	Broadcasting test patterns to multiple circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
59	Melanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding	Scan chain clustering for test power reduction.	DAC	2008	DBLP DOI BibTeX RDF	test, low power, design for test, scan design
59	Puneet Gupta 0001, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma	Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage.	ICCAD	2003	DBLP DOI BibTeX RDF
59	Nisar Ahmed, Mohammad Tehranipoor	Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique.	DFT	2005	DBLP DOI BibTeX RDF
58	Yu Huang 0005, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-Ju Hsieh, Yu-Ting Hung	Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault.	ITC	2003	DBLP DOI BibTeX RDF
57	Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici	Scan Architecture for Shift and Capture Cycle Power Reduction.	DFT	2002	DBLP DOI BibTeX RDF
57	Ozgur Sinanoglu, Alex Orailoglu	Test power reductions through computationally efficient, decoupled scan chain modifications.	IEEE Trans. Reliab.	2005	DBLP DOI BibTeX RDF
57	Ondrej Novák, Jiri Nosek	Test Pattern Decompression Using a Scan Chain.	DFT	2001	DBLP DOI BibTeX RDF	hardware test pattern generators, BIST, test pattern generation, scan design
57	Wei-Lun Wang, Kuen-Jong Lee	Accelerated test pattern generators for mixed-mode BIST environments.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	accelerated test pattern generators, mixed-mode BIST, pseudorandom patterns, deterministic patterns, scan-based built-in self-test, multiple sub-chains, multiple sequence generator, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, linear feedback shift registers, cost, test pattern generator, shift registers, test application time, scan chain, mixed analogue-digital integrated circuits, clock cycle, integrated circuit economics
56	Xiaodong Zhang 0010, Kaushik Roy 0001	Power Reduction in Test-Per-Scan BIST.	IOLTW	2000	DBLP DOI BibTeX RDF	Test-per-scan, Low Power BIST, Testing, Low Power, BIST, Weighted Random Pattern
55	Nahmsuk Oh, Rohit Kapur, Thomas W. Williams, Jim Sproch	Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture.	DATE	2003	DBLP DOI BibTeX RDF
55	Dong Xiang, Mingjing Chen, Jia-Guang Sun	Scan BIST with biased scan test signals.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	random testability, test signal, biased random testing, scan-based BIST
54	Ondrej Novák, Jiri Nosek	Test-per-Clock Testing of the Circuits with Scan.	IOLTW	2001	DBLP DOI BibTeX RDF
54	Ho Fai Ko, Nicola Nicolici	Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
53	Ozgur Sinanoglu	Low Cost Scan Test by Test Correlation Utilization.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	test correlation, scan architecture design, test data compression, scan-based testing
53	Xiaoding Chen, Michael S. Hsiao	An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
53	Irith Pomeranz, Sudhakar M. Reddy	Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs.	VTS	2007	DBLP DOI BibTeX RDF
53	Yu Huang 0005, Keith Gallie	Diagnosis of defects on scan enable and clock trees.	DATE	2006	DBLP DOI BibTeX RDF
53	Samantha Edirisooriya, Geetani Edirisooriya	Diagnosis of scan path failures.	VTS	1995	DBLP DOI BibTeX RDF	scan path failures, scan based diagnostic schemes, faulty circuits, logic circuitry, scan chain fault diagnosis, fault diagnosis, logic testing, integrated circuit testing, design for testability, combinational circuits, integrated logic circuits
52	Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy 0001	Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning.	ISQED	2005	DBLP DOI BibTeX RDF
52	Irith Pomeranz	Reducing Test Data Volume Using Random-Testable and Periodic-Testable Scan Chains in Circuits with Multiple Scan Chains.	ITC	2003	DBLP DOI BibTeX RDF
52	Nicola Nicolici, Bashir M. Al-Hashimi	Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Digital systems testing, design for test, low power circuits
49	Melanie Elm, Hans-Joachim Wunderlich	Scan Chain Organization for Embedded Diagnosis.	DATE	2008	DBLP DOI BibTeX RDF
49	Ozgur Sinanoglu, Philip Schremmer	Diagnosis, modeling and tolerance of scan chain hold-time violations.	DATE	2007	DBLP DOI BibTeX RDF
49	Puneet Gupta 0001, Andrew B. Kahng, Stefanus Mantik	A Proposal for Routing-Based Timing-Driven Scan Chain Ordering.	ISQED	2003	DBLP DOI BibTeX RDF
49	Seongmoon Wang, Wenlong Wei	A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture.	ASP-DAC	2007	DBLP DOI BibTeX RDF	peak current reduction, average power dissipation, clock tree construction, special scan cells, scan chain reordering, ATPG, scan designs
49	James Chien-Mo Li	Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Fault diagnosis, ATPG, scan chain
48	Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz	A Low Power Pseudo-Random BIST Technique.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	low power, BIST, scan, pseudo-random, peak power
48	Ozgur Sinanoglu, Alex Orailoglu	Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
48	Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz	A Low Power Pseudo-Random BIST Technique.	ICCD	2002	DBLP DOI BibTeX RDF
48	Li-Chung Hsu, Hung-Ming Chen	On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design.	ISQED	2006	DBLP DOI BibTeX RDF
48	Il-soo Lee, Yong Min Hur, Tony Ambler	The Efficient Multiple Scan Chain Architecture Reducing Power Dissipation and Test Time.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
48	Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng	Logic BIST with Scan Chain Segmentation.	ITC	2004	DBLP DOI BibTeX RDF
48	Erik Larsson, Zebo Peng	Test Scheduling and Scan-Chain Division under Power Constraint.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
47	Md. Saffat Quasem, Sandeep K. Gupta 0001	Designing Reconfigurable Multiple Scan Chains for Systems-on-Chip.	VTS	2004	DBLP DOI BibTeX RDF
47	Chauchin Su, Shyh-Jye Jou	Decentralized BIST Methodology for System Level Interconnects.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	interconnect, BIST, DFT, boundary scan
47	Meng Lu, Yvon Savaria, Bing Qiu 0003, Jacques Taillefer	IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale Integration.	DFT	2003	DBLP DOI BibTeX RDF
45	Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito	Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters.	DFT	2006	DBLP DOI BibTeX RDF
45	Ruifeng Guo, Srikanth Venkataraman	An algorithmic technique for diagnosis of faulty scan chains.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
45	Debdeep Mukhopadhyay, Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya	CryptoScan: A Secured Scan Chain Architecture.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
45	Joep Aerts, Erik Jan Marinissen	Scan chain design for test time reduction in core-based ICs.	ITC	1998	DBLP DOI BibTeX RDF
45	Yu-Ze Wu, Mango Chia-Tso Chao	Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes.	VTS	2008	DBLP DOI BibTeX RDF	signal transitions, correlation, reordering, scan-chain
44	Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar, Kenneth M. Butler	Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
44	Jeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic	Securing Designs against Scan-Based Side-Channel Attacks.	IEEE Trans. Dependable Secur. Comput.	2007	DBLP DOI BibTeX RDF	Security and Privacy Protection, Scan-Based Design, Secure Design, Reliability and Testing
44	Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici	Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
44	Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee	Test-point insertion: scan paths through functional logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
44	Ilia Polian, Bernd Becker 0001	Multiple Scan Chain Design for Two-Pattern Testing.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	scan chain insertion, delay testing, design for test, core-based test
44	Ilia Polian, Bernd Becker 0001	Multiple Scan Chain Design for Two-Pattern Testing.	VTS	2001	DBLP DOI BibTeX RDF	Scan chain insertion, Delay testing, Design for test, Core-based test
44	Samy Makar, Edward J. McCluskey	ATPG for scan chain latches and flip-flops.	VTS	1997	DBLP DOI BibTeX RDF	bistable element, scan chain circuit, combinational defect detection, algorithm, ATPG, automatic test pattern generation, automatic testing, stuck-at fault, flip-flop, latch, checking experiment
44	Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu	Low Power BIST with Smoother and Scan-Chain Reorder .	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
44	Yoshinobu Higami, Kozo Kinoshita	Design of partially parallel scan chain.	ED&TC	1997	DBLP DOI BibTeX RDF
44	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
44	Zaifu Zhang, Robert D. McLeod	An Efficient Multiple Scan Chain Testing Scheme.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
43	Seongmoon Wang, Srimat T. Chakradhar	A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF