Search results for "standby"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
198	Ing-Ray Chen, Farokh B. Bastani	Warm Standby in Hierarchically Structured Process-Control Programs.	IEEE Trans. Software Eng.	1994	DBLP DOI BibTeX RDF	hierarchically structured process-control programs, standby redundancy design space, process-control programs, cold standby, warm standby, hot standby, long-lived unmaintainable systems, burst hardware failures, simulated chemical batch reactor system, fault tolerant computing, software maintenance, software reliability, redundancy, system reliability, computer integrated manufacturing, process computer control
75	Vivek De	Leakage-tolerant design techniques for high performance processors.	ISPD	2002	DBLP DOI BibTeX RDF
70	Paul R. van der Meer, Arie van Staveren	Effectivity of standby-energy reduction techniques for deep sub-micron CMOS.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
70	Huang-Chen Lee, Chuan-Yu Cho, Yao-Min Fang, Bing-Jean Lee, Chung-Ta King	Exploiting the tradeoff between fast wakeup and long standby in event-monitoring WSN.	SenSys	2009	DBLP DOI BibTeX RDF	standby time, wireless sensor networks, low power, response time, duty cycle
64	Yu Wang 0002, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie 0001	Temperature-aware NBTI modeling and the impact of input vector control on performance degradation.	DATE	2007	DBLP DOI BibTeX RDF
59	Sumangali K. Srinivasan, Ramchandran Subramanian	Reliability analysis of a three unit warm standby redundant system with repair.	Ann. Oper. Res.	2006	DBLP DOI BibTeX RDF
59	Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy 0001	Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks.	ISLPED	1998	DBLP DOI BibTeX RDF
59	Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran	Fundamental Data Retention Limits in SRAM Standby Experimental Results.	ISQED	2008	DBLP DOI BibTeX RDF	standby, data retention, low power, SRAM, error control code
59	Shoun Matsunaga, Takahiro Hanyu, Hiromitsu Kimura, Takashi Nakamura, Hidemi Takasu	Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.35 micron, standby-power-free CAM, complementary ferroelectric-capacitor logic, CFC logic circuit, nonvolatile storage, ferroelectric CMOS, content-addressable memory
59	Geoffrey C.-F. Yeap	Leakage current in low standby power and high performance devices: trends and challenges.	ISPD	2002	DBLP DOI BibTeX RDF	gate tunneling leakage, low standby power, off-state sub-threshold leakage, system-on-a-ship (SoC), high performance, CMOS technology, leakage current
54	Shih-Hsu Huang, Chun-Hua Cheng	Timing driven power gating in high-level synthesis.	ASP-DAC	2009	DBLP DOI BibTeX RDF
53	David T. Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards	Emerging power management tools for processor design.	ISLPED	1998	DBLP DOI BibTeX RDF	low power CAD, standby leakage, power distribution
49	Huifang Qin, Animesh Kumar, Kannan Ramchandran, Jan M. Rabaey, Prakash Ishwar	Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation.	ISQED	2008	DBLP DOI BibTeX RDF	DRV, low power, ECC, leakage, SRAM, variation, low voltage, error tolerant
49	Bhupender Parashar, Gulshan Taneja	Reliability and Profit Evaluation of a PLC Hot Standby System Based on a Master-Slave Concept and Two Types of Repair Facilities.	IEEE Trans. Reliab.	2007	DBLP DOI BibTeX RDF
49	Dongwoo Lee, Harmander Deogun, David T. Blaauw, Dennis Sylvester	Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization.	DATE	2004	DBLP DOI BibTeX RDF
49	Joep L. W. Kessels, Paul Marston	Designing Asynchronous Standby Circuits for a Low-Power Pager.	ASYNC	1997	DBLP DOI BibTeX RDF	pager, loadable counter, synchronous/asynchronous, low-power, co-design
48	Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa	Automated selective multi-threshold design for ultra-low standby applications.	ISLPED	2002	DBLP DOI BibTeX RDF	standby leakage current, automated design, multi-threshold
43	Jun Wang 0001, Xiaoyu Yao, Huijun Zhu	Exploiting In-Memory and On-Disk Redundancy to Conserve Energy in Storage Systems.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	System architectures, Energy-aware systems, Secondary storage, integration and modeling, Storage hierarchies
43	Mingoo Seok, Scott Hanson, Dennis Sylvester, David T. Blaauw	Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design.	DAC	2007	DBLP DOI BibTeX RDF
43	Dongwoo Lee, David T. Blaauw, Dennis Sylvester	Static leakage reduction through simultaneous Vt/Tox and state assignment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
43	Gi-sung Lee	Duplex Method for Mobile Communication Systems.	MSN	2005	DBLP DOI BibTeX RDF
43	Kaviraj Chopra, Sarma B. K. Vrudhula	Implicit pseudo boolean enumeration algorithms for input vector control.	DAC	2004	DBLP DOI BibTeX RDF	power, CMOS, SAT, binary decision diagrams, leakage, symbolic methods
43	Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy 0001, Vivek De	Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
43	Tadahiro Kuroda, Takayasu Sakurai	Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
43	Baozhen Yu, Michael L. Bushnell	A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	power cutoff, standby current, stacking, leakage current, dynamic power
43	Nikhil Jayakumar, Sunil P. Khatri	An ASIC design methodology with predictably low leakage, using leakage-immune standard cells.	ISLPED	2003	DBLP DOI BibTeX RDF	standby current, leakage current, standard cells, MTCMOS
42	Seiji Miura, Kazushige Ayukawa, Takao Watanabe	A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU.	ISLPED	2001	DBLP DOI BibTeX RDF	SDRAM controller, active-standby mode, standby mode
38	S. Lakshminarayanan, J. Joung, Giri Narasimhan, Ravi Kapre, M. Slanina, J. Tung, Morgan Whately, C.-L. Hou, W.-J. Liao, S.-C. Lin, P.-G. Ma, C.-W. Fan, M.-C. Hsieh, F.-C. Liu, K.-L. Yeh, W.-C. Tseng, S. W. Lu	Standby power reduction and SRAM cell optimization for 65nm technology.	ISQED	2009	DBLP DOI BibTeX RDF
38	Joon Heo, Jihyuk Heo, Choong Seon Hong, Seok Bong Kang, Sang Soo Jeon	Standby Power Control Architecture in Context-Aware Home Networks.	APNOMS	2007	DBLP DOI BibTeX RDF
38	Kyung Ki Kim, Yong-Bin Kim	Optimal Body Biasing for Minimum Leakage Power in Standby Mode.	ISCAS	2007	DBLP DOI BibTeX RDF
38	Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran	Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM.	ISCAS	2007	DBLP DOI BibTeX RDF
38	Takeshi Nakatsuru, Koji Murakami, Hiroshi Sakai	Context-Aware Information Provision to the Mobile Phone Standby Screen.	MDM	2006	DBLP DOI BibTeX RDF
38	Antoni Wolski, Vilho Raatikka	Performance Measurement and Tuning of Hot-Standby Databases.	ISAS	2006	DBLP DOI BibTeX RDF
38	Khin Mi Mi Aung, Kiejin Park, Jong Sou Park	A Model of ITS Using Cold Standby Cluster.	ICADL	2005	DBLP DOI BibTeX RDF	Concepts and Models, Intrusion Tolerant System, Security, Cluster System, Rejuvenation
38	Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif	Approaches to run-time and standby mode leakage reduction in global buses.	ISLPED	2004	DBLP DOI BibTeX RDF	pulsed buses, leakage, repeaters, MTCMOS
38	Huifang Qin, Yu Cao, Dejan Markovic, Andrei Vladimirescu, Jan M. Rabaey	SRAM Leakage Suppression by Minimizing Standby Supply Voltage.	ISQED	2004	DBLP DOI BibTeX RDF
38	Qi Wang, Sarma B. K. Vrudhula	Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
38	Salvatore Distefano, Francesco Longo 0001, Marco Scarpa	Availability Assessment of HA Standby Redundant Clusters.	SRDS	2010	DBLP DOI BibTeX RDF	Dynamic Reliability, Standby Redundancy, High Availability Clusters
38	Barry R. Borgerson, Richard F. Freitas	A Reliability Model for Gracefully Degrading and Standby-Sparing Systems.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	gracefully degrading, resource exhaustion, solitary faults, space-domain multiple faults, standby sparing, time-domain multiple faults, Fault tolerance, reliability, PRIME
33	Jingyuan Shen, Jiawen Hu, Zhi-Sheng Ye 0001	Optimal switching policy for warm standby systems subjected to standby failure mode.	IISE Trans.	2020	DBLP DOI BibTeX RDF
33	Amit Manocha, Gulshan Taneja, Sukhvir Singh, Rahul Rishi	Modelling and analysis of two-unit hot standby database system with random inspection of standby unit.	Int. J. Math. Oper. Res.	2019	DBLP DOI BibTeX RDF
33	Yingchieh Ho, Chen Hsu	Standby power reduction using dynamic standby control with voltage keeper.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
33	Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki	A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
33	Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Yasuhisa Shimazaki	A 0.41µA standby leakage 32Kb embedded SRAM with Low-Voltage resume-standby utilizing all digital current comparator in 28nm HKMG CMOS.	VLSIC	2012	DBLP DOI BibTeX RDF
33	Salvatore Distefano	The standby engineering: classification and quantification of standby in reliability.	Int. J. Syst. Assur. Eng. Manag.	2011	DBLP DOI BibTeX RDF
33	Kuo-Hsiung Wang, Wen-Li Dong, Jyh-Bin Ke	Comparison of reliability and the availability between four systems with warm standby components and standby switching failures.	Appl. Math. Comput.	2006	DBLP DOI BibTeX RDF
33	Makoto Ishikawa, Tatsuya Kamei, Yuki Kondo, Masanao Yamaoka, Yasuhisa Shimazaki, Motokazu Ozawa, Saneaki Tamaki, Mikio Furuyama, Tadashi Hoshi, Fumio Arakawa, Osamu Nishii, Kenji Hirose, Shinichi Yoshioka, Toshihiro Hattori	A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones.	IEICE Trans. Electron.	2005	DBLP DOI BibTeX RDF
33	Shunji Osaki, Toshio Nakagawa	On a Two-Unit Standby Redundant System with Standby Failure.	Oper. Res.	1971	DBLP DOI BibTeX RDF
32	Anuj Pushkarna, Hamid Mahmoodi	Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	reliability, aging, SRAM, power gating
32	Shahram Ghandeharizadeh, Andrew Goodney, Chetan Sharma, Chris Bissell, Felipe Carino, Naveen Nannapaneni, Alex Wergeles, Aber Whitcomb	Taming the storage dragon: the adventures of hoTMaN.	SIGMOD Conference	2009	DBLP DOI BibTeX RDF	data availability, storage area networks
32	Yu Wang 0002, Xiaoming Chen 0003, Wenping Wang, Varsha Balakrishnan, Yu Cao 0001, Yuan Xie 0001, Huazhong Yang	On the efficacy of input Vector Control to mitigate NBTI effects and leakage power.	ISQED	2009	DBLP DOI BibTeX RDF
32	Ekow J. Otoo, Doron Rotem, Shih-Chiang Tsao	Energy Smart Management of Scientific Data.	SSDBM	2009	DBLP DOI BibTeX RDF	Scientific workload, Performance guaranttee, Power management, File allocation, Disk storage
32	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang	Run-time power gating of on-chip routers using look-ahead routing.	ASP-DAC	2008	DBLP DOI BibTeX RDF
32	Tim Tuan, Arifur Rahman, Satyaki Das, Steven Trimberger, Sean Kao	A 90-nm Low-Power FPGA for Battery-Powered Applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
32	Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura	A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation.	ASP-DAC	2007	DBLP DOI BibTeX RDF
32	Afshin Nourivand, Chunyan Wang 0004, M. Omair Ahmad	An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM.	ISCAS	2007	DBLP DOI BibTeX RDF
32	Subhomoy Chattopadhyay, Rakesh Patel	Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller.	VLSI Design	2007	DBLP DOI BibTeX RDF
32	Tim Tuan, Sean Kao, Arifur Rahman, Satyaki Das, Steven Trimberger	A 90nm low-power FPGA for battery-powered applications.	FPGA	2006	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, low-power design, programmable logic
32	Markus Bajohr, Tiziana Margaria, Bernhard Steffen	Service Based Enabling Service Availability in the MaTRICS: A Model-Driven Approach.	ISoLA	2006	DBLP DOI BibTeX RDF
32	Xiaoyu Yao, Jun Wang 0001	RIMAC: a novel redundancy-based hierarchical cache architecture for energy efficient, high performance storage systems.	EuroSys	2006	DBLP DOI BibTeX RDF	power management, cache management, disk storage
32	Kiyotaka Imai, Yasushi Yamagata, Sadaaki Masuoka, Naohiko Kimuzuka, Yuri Yasuda, Mitsuhiro Togo, Masahiro Ikeda, Yasutaka Nakashiba	Device technology for body biasing scheme.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
32	Sergey Romanovsky, Arun Achyuthan, Sreedhar Natarajan, Wing Leung	Leakage Reduction techniques in a 0.13um SRAM Cell.	VLSI Design	2004	DBLP DOI BibTeX RDF
32	Ge Yang 0004, Zhongda Wang, Sung-Mo Kang	Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies.	VLSI Design	2004	DBLP DOI BibTeX RDF
32	Benton H. Calhoun, Frank Honoré, Anantha P. Chandrakasan	Design methodology for fine-grained leakage control in MTCMOS.	ISLPED	2003	DBLP DOI BibTeX RDF	fine-grain sleep regions, sneak leakage, low power, design methodology, leakage, circuit design, sleep mode, MTCMOS
32	Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Rajendran Panda, David T. Blaauw	Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
32	Aveek Sarkar, Shen Lin, Kai Wang	A methodology for analysis and verification of power gated circuits with correlated results.	ISLPED	2007	DBLP DOI BibTeX RDF	RedHawk, standby leakage current, design, verification, analysis, power gate, MTCMOS
32	Shunzo Yamashita, Takanori Shimura, Kiyoshi Aiki, Koji Ara, Yuji Ogata, Isamu Shimokawa, Takeshi Tanaka, Hiroyuki Kuriyama, Kazuyuki Shimada, Kazuo Yano	A 15 - 15 mm, 1 µA, reliable sensor-net module: enabling application-specific nodes.	IPSN	2006	DBLP DOI BibTeX RDF	15 - 15 mm, pulse sensing, standby current of 1 ?A, sensor networks, ZigBee, IEEE 802.15.4, sensor nodes, health care system
32	Edmond J. Vanderperre, Stanislav S. Makhanov	A Markov time related to a robot-safety device system.	4OR	2005	DBLP DOI BibTeX RDF	safety device, cold standby, recovery time, Weibull repair, Robot, availability
32	Ravindra Jejurikar, Rajesh K. Gupta 0001	Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems.	ISLPED	2004	DBLP DOI BibTeX RDF	critical speed, lowpower, procrastication, resource standby energy, real-time systems, DVS, EDF scheduling
32	David Scott, Shaoping Tang, Song Zhao, Mahalingam Nandakumar	Device Physics Impact on Low Leakage, High Speed DSP Design Techniques (invited).	ISQED	2002	DBLP DOI BibTeX RDF	standby, GIDL, leakage, tunneling, subthreshold, current
27	Adam C. Cabe, Zhenyu Qi, Mircea R. Stan	Stacking SRAM banks for ultra low power standby mode operation.	DAC	2010	DBLP DOI BibTeX RDF	stacked SRAM, low-power memory
27	Xing Qiao, Zhaoxing Li, Dan Ma	Exponential Asymptotic Stability of a Two-Unit Standby Redundant Electronic Equipment System under Human Failure.	ISNN (1)	2009	DBLP DOI BibTeX RDF	Exponential asymptotic stability, Quasi-compact operator, c 0-semigroup, Electronic equipment system
27	Alireza Ejlali, Bashir M. Al-Hashimi, Petru Eles	A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	reliability, energy minimization, hard real-time systems
27	Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry	Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units.	MICRO	2006	DBLP DOI BibTeX RDF
27	Thomas Janik, Eric Liau, Harald Lorenz, Manfred Menke, Eckehard Plaettner, Joerg Schweden, Helmut Seitz, Esther Vega-Ordonez	A 1.8V p(seudo)SRAM using standard 140nm DRAM technology with self adapting clocked standby operation.	ISCAS	2006	DBLP DOI BibTeX RDF
27	Lawrence T. Clark, M. Morrow, W. Brown	Reverse-body bias and supply collapse for low effective standby power.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
27	Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty	Managing standby and active mode leakage power in deep sub-micron design.	ISLPED	2004	DBLP DOI BibTeX RDF	SRAM leakage control, TGSRAM, battery lifetime, drowsy mode, thick gate shadow latch, transistor leakage, MTCMOS
27	Amir Amirabadi, Javid Jaffari, Ali Afzali-Kusha, Mehrdad Nourani, Ali Khaki-Firooz	Leakage current reduction by new technique in standby mode.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	subthreshold current, low power, leakage current, digital integrated circuits, static power
27	Mircea R. Stan	Low threshold CMOS circuits with low standby current.	ISLPED	1998	DBLP DOI BibTeX RDF
21	Faraz Ahmad, T. N. Vijaykumar	Joint optimization of idle and cooling power in data centers while maintaining response time.	ASPLOS	2010	DBLP DOI BibTeX RDF	cooling power, idle power, power management, response time, data center
21	Derek Hower, Pablo Montesinos, Luis Ceze, Mark D. Hill, Josep Torrellas	Two hardware-based approaches for deterministic multiprocessor replay.	Commun. ACM	2009	DBLP DOI BibTeX RDF
21	Feng Wang, Jie Qiu 0001, Jie Yang, Bo Dong 0001, Xin Hui Li, Ying Li 0012	Hadoop high availability through metadata replication.	CloudDB@CIKM	2009	DBLP DOI BibTeX RDF	hadoop
21	Ekow J. Otoo, Doron Rotem, Shih-Chiang Tsao	Analysis of trade-off between power saving and response time in disk storage systems.	IPDPS	2009	DBLP DOI BibTeX RDF
21	Lawrence Leinweber, Swarup Bhunia	Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction.	DATE	2008	DBLP DOI BibTeX RDF
21	Tak H. Ning	GLSVLSI 2008 invited/keynote talk.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	soi, cmos scaling
21	Lin Huang 0002, Qiang Xu 0001	On Modeling the Lifetime Reliability of Homogeneous Manycore Systems.	PRDC	2008	DBLP DOI BibTeX RDF
21	Charbel J. Akl, Magdy A. Bayoumi	Self-Sleep Buffer for Distributed MTCMOS Design.	VLSI Design	2008	DBLP DOI BibTeX RDF
21	Seungwhun Paik, Youngsoo Shin	Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements.	DAC	2008	DBLP DOI BibTeX RDF	sleep vector, zigzag power gating, low power, leakage current, standard-cell
21	Nikhil Jayakumar, Sunil P. Khatri	A Predictably Low-Leakage ASIC Design Style.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
21	Kunhyuk Kang, Haldun Kufluoglu, Kaushik Roy 0001, Muhammad Ashraful Alam	Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
21	Masayuki Murakami	Fault tolerance design for computers used in humanoid robots.	IROS	2007	DBLP DOI BibTeX RDF
21	Subhomoy Chattopadhyay	Low power design techniques for nanometer design processes: 65 nm and smaller.	SBCCI	2007	DBLP DOI BibTeX RDF	65 nm, low power, embedded design
21	Zhiyu Liu, Volkan Kursun	Charge Recycling MTCMOS for Low Energy Active/Sleep Mode Transitions.	ISCAS	2007	DBLP DOI BibTeX RDF
21	Chanseok Hwang, Peng Rong, Massoud Pedram	Sleep transistor distribution in row-based MTCMOS designs.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	leakage minimization, placement, MTCMOS
21	Tarun Sairam, Wei Zhao, Yu Cao 0001	Optimizing finfet technology for high-speed and low-power design.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	power, energy, variations, speed, threshold voltage, FinFET, noise margin
21	Zhiyu Liu, Volkan Kursun	Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS.	ISQED	2007	DBLP DOI BibTeX RDF	Multi-threshold voltage CMOS, gated power, gated ground, sleep switch, subthreshold leakage, charge recycling
21	Hong Luo, Yu Wang 0002, Ku He, Rong Luo, Huazhong Yang, Yuan Xie 0001	Modeling of PMOS NBTI Effect Considering Temperature Variation.	ISQED	2007	DBLP DOI BibTeX RDF
21	Chia-Tai Tsai, Rong-Hong Jan, Chien Chen, Chia-Yuan Huang	Implementation of Highly Available OSPF Router on ATCA.	PRDC	2007	DBLP DOI BibTeX RDF
21	Lava P. Kumar, Baquer Mazhari	Optimum Supply Voltages for Minimization of Leakage Currents in SRAM in Stand-by Mode.	VLSI Design	2007	DBLP DOI BibTeX RDF
21	Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo	Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF