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Found 6 publication records. Showing 6 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
91 | Ron Gabor, Shlomo Weiss, Avi Mendelson |
Fairness enforcement in switch on event multithreading. |
ACM Trans. Archit. Code Optim. |
2007 |
DBLP DOI BibTeX RDF |
SOE, Switch on Event multithreading, coarse-grained multithreading, weighted speedup, performance, fairness, throughput, multithreading |
72 | Ron Gabor, Shlomo Weiss, Avi Mendelson |
Fairness and Throughput in Switch on Event Multithreading. |
MICRO |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Perry H. Wang, Jamison D. Collins, Hong Wang 0003, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen |
Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform. |
ASPLOS |
2004 |
DBLP DOI BibTeX RDF |
DB2 database, cache miss prefetching, itanium processor, switch-on-event, multithreading, helper thread, PAL |
8 | Ron Gabor, Avi Mendelson, Shlomo Weiss |
Service level agreement for multithreaded processors. |
ACM Trans. Archit. Code Optim. |
2009 |
DBLP DOI BibTeX RDF |
performance, fairness, throughput, power, Service level agreement |
8 | Perry H. Wang, Jamison D. Collins, Hong Wang 0003, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen |
Helper Threads via Virtual Multithreading. |
IEEE Micro |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Tomasz Madajczak |
An Optimal Abstraction Model for Hardware Multithreading in Modern Processor Architectures. |
PARELEC |
2004 |
DBLP DOI BibTeX RDF |
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