Search results for "system-on-chips"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
31	Oussama Laouamri, Chouki Aktouf	Towards a Complete SNMP-Based Supervision of System-on-Chips.	J. Netw. Syst. Manag.	2005	DBLP DOI BibTeX RDF	P1500 wrapper, System-on-chips, Network management, SNMP, Design-for-test
29	Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg, Alberto García Ortiz, Thilo Pionteck	System-level optimization of Network-on-Chips for heterogeneous 3D System-on-Chips.	CoRR	2019	DBLP BibTeX RDF
29	Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg, Alberto García Ortiz, Thilo Pionteck	System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips.	ICCD	2019	DBLP DOI BibTeX RDF
23	Xiaoyu Ruan, Rajendra S. Katti	Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	system-on-chips, automatic test pattern generator, Automatic test equipment, test data compression, embedded core testing, run-length coding
21	Oussama Laouamri, Chouki Aktouf	Enhancing Testability of System on Chips Using Network Management Protocols.	DATE	2004	DBLP DOI BibTeX RDF
21	Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Toshio Isomura, Kazuo Satou	Trace-driven workload simulation method for Multiprocessor System-On-Chips.	DAC	2009	DBLP DOI BibTeX RDF	MPSoC architecture exploration, simulation, performance estimation, workload model
21	Takefumi Yoshikawa, Takashi Hirata, Tsuyoshi Ebuchi, Toru Iwata, Yukio Arima, Hiroyuki Yamauchi	An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
21	Rajesh Tiwari, Abhijeet Shrivastava, Mahit Warhadpande, Srivaths Ravi 0001, Rubin A. Parekhji	A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips.	VTS	2008	DBLP DOI BibTeX RDF	Tester, ATPG, Estimation, ATE, Test Time, Test Data Volume
21	Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara	Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses.	ASP-DAC	2007	DBLP DOI BibTeX RDF
21	Riccardo Mariani, Gabriele Boschi	A systematic approach for Failure Modes and Effects Analysis of System-On-Chips.	IOLTS	2007	DBLP DOI BibTeX RDF
21	Santanu Chattopadhyay, K. Sudarsana Reddy	Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips.	VLSI Design	2003	DBLP DOI BibTeX RDF
21	Kazuhiko Iijima, Armagan Akar, Charlie McDonald, Dwayne Burek	Embedded Test Solution as a Breakthrough in Reducing Cost of Test for System on Chips.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
21	Yi Zhao, Li Chen, Sujit Dey	On-Line Testing of Multi-Source Noise-Induced Errors on the Interconnects and Buses of System-on-Chips.	ITC	2002	DBLP DOI BibTeX RDF
17	Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis	Performance Improvements from Partitioning Applications to FPGA Hardware in Embedded SoCs.	J. Supercomput.	2006	DBLP DOI BibTeX RDF	embedded system-on-chips, kernel identification, FPGA, hardware/software partitioning, performance improvement
16	Subrat Mishra, Sankatali Venkateswarlu, Bjorn Vermeersch, Moritz Brunion, Melina Lofrano, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Gaspard Hiblot, Geert Van der Plas, Pieter Weckx, Geert Hellings, James Myers, Francky Catthoor, Julien Ryckaert	Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs).	IRPS	2023	DBLP DOI BibTeX RDF
16	Huajuan Zhang, Hao Xiao, Ning Wu	A system-level design of MapReduce-based embedded multiprocessor system-on-chips.	ISOCC	2016	DBLP DOI BibTeX RDF
16	Sungchan Kim, Soonhoi Ha	System-level performance analysis of multiprocessor system-on-chips by combining analytical model and execution time variation.	Microprocess. Microsystems	2014	DBLP DOI BibTeX RDF
16	Jia Huang	Towards an Integrated Framework for Reliability-Aware Embedded System Design on Multiprocessor System-on-Chips.		2014	RDF
16	Wen-Tsai Sung, Jui-Ho Chen, Kung-Wei Chang	Study on a Real-Time BEAM System for Diagnosis Assistance Based on a System on Chips Design.	Sensors	2013	DBLP DOI BibTeX RDF
16	Guanyi Sun, Shengnan Xu, Xu Wang, Dawei Wang, Eugene Tang, Yangdong Deng, Sun Chan	A High-Throughput, High-Accuracy System-Level Simulation Framework for System on Chips.	VLSI Design	2011	DBLP DOI BibTeX RDF
16	Yuxin Wang, Martin Margala	New Embedded Core Testing for System-on-Chips and System-in-Packages.	CCECE	2006	DBLP DOI BibTeX RDF
16	Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla	System Level Design Methodology for System On Chips using Multi-Threaded Graphs.	SoCC	2005	DBLP DOI BibTeX RDF
14	Emanuele Parisi, Alberto Musa, Maicol Ciani, Francesco Barchi, Davide Rossi, Andrea Bartolini, Andrea Acquaviva	Assessing the Performance of OpenTitan as Cryptographic Accelerator in Secure Open-Hardware System-on-Chips.	CoRR	2024	DBLP DOI BibTeX RDF
14	Ismet Dagli, Mehmet E. Belviranli	Shared Memory-contention-aware Concurrent DNN Execution for Diversely Heterogeneous System-on-Chips.	PPoPP	2024	DBLP DOI BibTeX RDF
14	Francesco Angione, Davide Appello, Paolo Bernardi, Andrea Calabrese, Stefano Quer, Matteo Sonza Reorda, Vincenzo Tancorre, Roberto Ugioli	A Toolchain to Quantify Burn-In Stress Effectiveness on Large Automotive System-on-Chips.	IEEE Access	2023	DBLP DOI BibTeX RDF
14	Ahmad Patooghy, Mehdi Elahi, Maral Filvan Torkaman, Sara Sezavar Dokhtfaroughi, Ramin Rajaei	Addressing Benign and Malicious Crosstalk in Modern System-on-Chips.	IEEE Access	2023	DBLP DOI BibTeX RDF
14	Siwakorn Thongmark, Woradorn Wattanapanitch	Design of a High-Efficiency Low-Ripple Buck Converter for Low-Power System-On-Chips.	IEEE Access	2023	DBLP DOI BibTeX RDF
14	Toygun Basaklar, A. Alper Goksoy, Anish Krishnakumar, Suat Gumussoy, Ümit Y. Ogras	DTRL: Decision Tree-based Multi-Objective Reinforcement Learning for Runtime Task Scheduling in Domain-Specific System-on-Chips.	ACM Trans. Embed. Comput. Syst.	2023	DBLP DOI BibTeX RDF
14	Ismet Dagli, Mehmet E. Belviranli	Shared Memory-contention-aware Concurrent DNN Execution for Diversely Heterogeneous System-on-Chips.	CoRR	2023	DBLP DOI BibTeX RDF
14	Carsten Heinz, Andreas Koch 0001	$\mathrm {DD\text {-}MPU}$: Dynamic and Distributed Memory Protection Unit for Embedded System-on-Chips.	SAMOS	2023	DBLP DOI BibTeX RDF
14	Sujan Kumar Saha, Abigail N. Butka, Muhammed Kawser Ahmed, Christophe Bobda	OpenTitan based Multi-Level Security in FPGA System-on-Chips.	ICFPT	2023	DBLP DOI BibTeX RDF
14	Romain Cayre, Damien Cauquil, Aurélien Francillon	ESPwn32: Hacking with ESP32 System-on-Chips.	SP (Workshops)	2023	DBLP DOI BibTeX RDF
14	Francesco Restuccia 0002, Ryan Kastner	Cut and Forward: Safe and Secure Communication for FPGA System on Chips.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
14	Tessil Thomas, Bharath Venkatasubramanian, Dinesh Sthapit, Christopher Gray, Atresh Gummadavelly, Janick Bergeron, Pankaj Mehta, Prabu Thangamuthu	Left-shifter: A pre-silicon framework for usage model based performance verification of the PCIe interface in server processor system on chips.	ISPASS	2022	DBLP DOI BibTeX RDF
14	Yuanchao Xu 0001, Mehmet Esat Belviranli, Xipeng Shen, Jeffrey S. Vetter	PCCS: Processor-Centric Contention-aware Slowdown Model for Heterogeneous System-on-Chips.	MICRO	2021	DBLP DOI BibTeX RDF
14	Zhe Jiang 0004, Neil C. Audsley, Dayu Shill, Kecheng Yang 0001, Nathan Fisher, Zheng Dong 0002	Brief Industry Paper: AXI-InterconnectRT: Towards a Real-Time AXI-Interconnect for System-on-Chips.	RTAS	2021	DBLP DOI BibTeX RDF
14	Tim Hotfilter, Julian Höfer, Fabian Kreß, Fabian Kempf, Jürgen Becker 0001	FLECSim-SoC: A Flexible End-to-End Co-Design Simulation Framework for System on Chips.	SoCC	2021	DBLP DOI BibTeX RDF
14	Yasser S. Abdalla	A novel flash-like all-metal-oxide semiconductor analog-to-digital converter suitable for system on chips systems.	Int. J. Circuit Theory Appl.	2020	DBLP DOI BibTeX RDF
14	Andrea Floridia, Tzamn Melendez Carmona, Davide Piumatti, Annachiara Ruospo, Ernesto Sánchez 0001, Sergio de Luca, Rosario Martorana, Mose Alessandro Pernice	Deterministic Cache-based Execution of On-line Self-Test Routines in Multi-core Automotive System-on-Chips.	DATE	2020	DBLP DOI BibTeX RDF
14	Manting Yao, Weina Yuan, Nan Wang 0003, Zeyu Zhang, Yuan Qiu 0007, Yichuan Liu	SS3: Security-Aware Vendor-Constrained Task Scheduling for Heterogeneous Multiprocessor System-on-Chips.	ICNSC	2020	DBLP DOI BibTeX RDF
14	Nisha Jacob Kabakci	Hardware Trojans and their Security Impact on Reconfigurable System-on-Chips.		2020	RDF
14	Mohammad Motamedi, Daniel D. Fong, Soheil Ghiasi	Cappuccino: Efficient CNN Inference Software Synthesis for Mobile System-on-Chips.	IEEE Embed. Syst. Lett.	2019	DBLP DOI BibTeX RDF
14	Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Paolo Ienne	Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips.	IEEE Access	2019	DBLP DOI BibTeX RDF
14	Samet E. Arda, Anish Krishnakumar, A. Alper Goksoy, Joshua Mack, Nirmal Kumbhare, Anderson L. Sartor, Ali Akoglu, Radu Marculescu, Ümit Y. Ogras	Work-in-Progress: A Simulation Framework for Domain-Specific System-on-Chips.	CoRR	2019	DBLP BibTeX RDF
14	Shiqing Li, Yixun Wei, Lei Ju 0001	Automatic data placement for CPU-FPGA heterogeneous multiprocessor System-on-Chips.	DATE	2019	DBLP DOI BibTeX RDF
14	Regina Marcela Ivo, Daniel M. Muñoz	RTRLib: A High-Level Modeling Tool for the Implementation of Dynamically Partial Reconfigurable System-on-Chips.	ReConFig	2019	DBLP DOI BibTeX RDF
14	Samet E. Arda, Anish Krishnakumar, A. Alper Goksoy, Joshua Mack, Nirmal Kumbhare, Anderson L. Sartor, Ali Akoglu, Radu Marculescu, Ümit Y. Ogras	A simulation framework for domain-specific system-on-chips: work-in-progress.	CODES+ISSS	2019	DBLP DOI BibTeX RDF
14	Ahmed M. Y. Ibrahim, Hans G. Kerkhoff	An On-Chip IEEE 1687 Network Controller for Reliability and Functional Safety Management of System-on-Chips.	ITC-Asia	2019	DBLP DOI BibTeX RDF
14	Ahmed M. Y. Ibrahim, Hans G. Kerkhoff	DARS: An EDA Framework for Reliability and Functional Safety Management of System-on-Chips.	ITC	2019	DBLP DOI BibTeX RDF
14	Andrea Floridia, Davide Piumatti, Annachiara Ruospo, Ernesto Sánchez 0001, Sergio de Luca, Rosario Martorana	A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-Chips.	ITC	2019	DBLP DOI BibTeX RDF
14	Jan Moritz Joseph, Dominik Ermel, Tobias Drewes, Lennart Bamberg, Alberto García-Ortiz, Thilo Pionteck	Area Optimization with Non-Linear Models in Core Mapping for System-on-Chips.	MOCAST	2019	DBLP DOI BibTeX RDF
14	Giovanni Pietro Seu	Exploiting All-Programmable System on Chips for Closed-Loop Real-Time Neural Interfaces.		2019	RDF
14	Nan Wang 0003, Manting Yao, Dongxu Jiang, Song Chen 0001, Yu Zhu	Security-Driven Task Scheduling for Multiprocessor System-on-Chips with Performance Constraints.	ISVLSI	2018	DBLP DOI BibTeX RDF
14	Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne	LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
14	Chia-Yin Liu, Cheng-En Wu, Yi-Jung Chen	Thermal-aware task and data co-allocation for multi-processor system-on-chips with 3D-stacked memories.	RACS	2018	DBLP DOI BibTeX RDF
14	Georg Sigl, Mathieu Gross, Michael Pehl	Where Technology Meets Security: Key Storage and Data Separation for System-on-Chips.	ESSCIRC	2018	DBLP DOI BibTeX RDF
14	Yvan Debizet, Guénolé Lallement, Fady Abouzeid, Philippe Roche, Jean-Luc Autran	Q-Learning-based Adaptive Power Management for IoT System-on-Chips with Embedded Power States.	ISCAS	2018	DBLP DOI BibTeX RDF
14	Vasileios Tenentes, Daniele Rossi 0001, Bashir M. Al-Hashimi	Collective-Aware System-on-Chips for Dependable IoT Applications.	IOLTS	2018	DBLP DOI BibTeX RDF
14	Mohammad Saber Golanbari, Mehdi Baradaran Tahoori	Runtime adjustment of IoT system-on-chips for minimum energy operation.	DAC	2018	DBLP DOI BibTeX RDF
14	Qi Tang 0002, Shang-Feng Wu, Jun-Wu Shi, Jibo Wei	Optimization of Duplication-Based Schedules on Network-on-Chip Based Multi-Processor System-on-Chips.	IEEE Trans. Parallel Distributed Syst.	2017	DBLP DOI BibTeX RDF
14	Mohammad Motamedi, Daniel D. Fong, Soheil Ghiasi	Cappuccino: Efficient Inference Software Synthesis for Mobile System-on-Chips.	CoRR	2017	DBLP BibTeX RDF
14	Michael Bromberger, Steffen Ehrle, Michael Scharrer, Lukas Erlinghagen, Jens Schick	OpenCL-Based 6D-Vision on Heterogeneous System on Chips.	ARCS	2017	DBLP DOI BibTeX RDF
14	Xiaokun Yang, Wujie Wen	Design of a pre-scheduled data bus for advanced encryption standard encrypted system-on-chips.	ASP-DAC	2017	DBLP DOI BibTeX RDF
14	Dongyoun Yi, Taewhan Kim	Switch cell optimization of power-gated modern system-on-chips.	ICCAD	2017	DBLP DOI BibTeX RDF
14	Nima Taherinejad, Muhammad Ali Shami, Sai Manoj P. D.	Self-aware sensing and attention-based data collection in Multi-Processor System-on-Chips.	NEWCAS	2017	DBLP DOI BibTeX RDF
14	Christophe Eychenne, Yervant Zorian	An effective functional safety infrastructure for system-on-chips.	IOLTS	2017	DBLP DOI BibTeX RDF
14	Ahmed Ibrahim 0001, Hans G. Kerkhoff	A cost-efficient dependability management framework for self-aware system-on-chips based on IEEE 1687.	IOLTS	2017	DBLP DOI BibTeX RDF
14	Takao Oshita, Joseph Shor, David E. Duarte, Avner Kornfeld, George L. Geannopoulos, Jonathan Douglas, Nasser A. Kurd	A Compact First-Order ΣΔ Modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
14	Stefan Gehrer, Georg Sigl	Area-Efficient PUF-Based Key Generation on System-on-Chips with FPGAs.	J. Circuits Syst. Comput.	2016	DBLP DOI BibTeX RDF
14	Hao Xiao, Huajuan Zhang, Fen Ge, Ning Wu	A MapReduce architecture for embedded multiprocessor system-on-chips.	IEICE Electron. Express	2016	DBLP DOI BibTeX RDF
14	Grigor Tshagharyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian	Securing test infrastructure of system-on-chips.	EWDTS	2016	DBLP DOI BibTeX RDF
14	Yidi Liu, Benjamin Carrión Schäfer	Optimization of behavioral IPs in multi-processor system-on-chips.	ASP-DAC	2016	DBLP DOI BibTeX RDF
14	Mahmoud Momtazpour, Omid Assare, Negar Rahmati, Amirali Boroumand, Saeid Barati 0001, Maziar Goudarzi	Yield-driven design-time task scheduling techniques for multi-processor system on chips under process variation: a comparative study.	IET Comput. Digit. Tech.	2015	DBLP DOI BibTeX RDF
14	Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman 0001	Optimisation of test architecture in three-dimensional stacked integrated circuits for partial stack/complete stack using hard system-on-chips.	IET Comput. Digit. Tech.	2015	DBLP DOI BibTeX RDF
14	Ian Gray, Gary Plumbridge, Neil C. Audsley	Toolchain-based approach to handling variability in embedded multiprocessor system on chips.	IET Comput. Digit. Tech.	2015	DBLP DOI BibTeX RDF
14	Hend Affes	Modélisation au niveau transactionnel de l'architecture et du contrôle relatifs à la gestion d'énergie de systèmes sur puce. (TLM modelling of architecture and control of power management structure for system on chips).		2015	RDF
14	Govindarajalu Bakthavatsalam, K. M. Mehata	A Case for Hybrid Instruction Encoding for Reducing Code Size in Embedded System-on-Chips based on RISC Processor Cores.	J. Comput. Sci.	2014	DBLP DOI BibTeX RDF
14	Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran	Performance Estimation of Pipelined MultiProcessor System-on-Chips (MPSoCs).	IEEE Trans. Parallel Distributed Syst.	2014	DBLP DOI BibTeX RDF
14	Yi Wang 0003, Zili Shao, Henry C. B. Chan, Duo Liu, Yong Guan	Memory-Aware Task Scheduling with Communication Overhead Minimization for Streaming Applications on Bus-Based Multiprocessor System-on-Chips.	IEEE Trans. Parallel Distributed Syst.	2014	DBLP DOI BibTeX RDF
14	David Lin, Ted Hong, Yanjing Li, Eswaran S, Sharad Kumar, Farzan Fallah, Nagib Hakim, Donald S. Gardner, Subhasish Mitra	Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
14	Giovanni Bruni, Paolo Rech, Lucas A. Tambara, Gabriel L. Nazar, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis 0001, Alessandro Paccagnella	Power dissipation effects on 28nm FPGA-based System on Chips neutron sensitivity.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
14	Francesco Paterna, Joe Zanotelli, Tajana Simunic Rosing	Ambient variation-tolerant and inter components aware thermal management for mobile system on chips.	DATE	2014	DBLP DOI BibTeX RDF
14	Meng-Ling Tsai, Yi-Jung Chen, Yi-Ting Chen, Ru-Hua Chang	Scenario-aware data placement and memory area allocation for Multi-Processor System-on-Chips with reconfigurable 3D-stacked SRAMs.	DATE	2014	DBLP DOI BibTeX RDF
14	Seung-Hwan Song, Ki Chul Chun, Chris H. Kim	A Logic-Compatible Embedded Flash Memory for Zero-Standby Power System-on-Chips Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
14	Nadia Nedjah, Lech Józwiak, Luiza de Macedo Mourelle	Application-specific processors and system-on-chips for embedded and pervasive applications.	Microprocess. Microsystems	2013	DBLP DOI BibTeX RDF
14	Dionysios Diamantopoulos, Kostas Siozios, Efstathios Sotiriou-Xanthopoulos, George Economakos, Dimitrios Soudris	HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips.	IPDPS Workshops	2013	DBLP DOI BibTeX RDF
14	Yanjing Li, Eric Cheng, Samy Makar, Subhasish Mitra	Self-repair of uncore components in robust system-on-chips: An OpenSPARC T2 case study.	ITC	2013	DBLP DOI BibTeX RDF
14	Xin An	Conception et contrôle de haut niveau pour les systèmes sur puce multiprocesseurs adaptatifs. (High level design and control of adaptive multiprocessor system-on-chips).		2013	RDF
14	Jaehwan John Lee, Xiang Xiao	Instant Multiunit Resource Hardware Deadlock Detection Scheme for System-on-Chips.	ACM Trans. Embed. Comput. Syst.	2012	DBLP DOI BibTeX RDF
14	Franco Fiori	On the use of high-impedance power supplies to reduce the substrate switching noise in system-on-chips.	Microelectron. Reliab.	2012	DBLP DOI BibTeX RDF
14	Hans G. Kerkhoff, Yong Zhao	The design of dependable flexible multi-sensory System-on-Chips for security applications.	DDECS	2012	DBLP DOI BibTeX RDF
14	Falko Guderian, Rainer Schaffer, Gerhard P. Fettweis	Administration- and communication-aware IP core mapping in scalable multiprocessor system-on-chips via evolutionary computing.	IEEE Congress on Evolutionary Computation	2012	DBLP DOI BibTeX RDF
14	Chao Wang 0003, Xi Li 0003, Peng Chen 0004, Xiaojing Feng, Junneng Zhang, Xuehai Zhou	Detecting Data Hazards in Multi-Processor System-on-Chips on FPGA.	IPDPS Workshops	2012	DBLP DOI BibTeX RDF
14	Adán Kohler, Juan Manuel Castillo-Sanchez, Joachim Gross, Martin Radetzki	Minimal MPI as programming interface for multicore System-on-Chips.	FDL	2012	DBLP BibTeX RDF
14	Amir Masoud Gharehbaghi, Masahiro Fujita	Transaction-based post-silicon debug of many-core System-on-Chips.	ISQED	2012	DBLP DOI BibTeX RDF
14	Brandon Noia, Krishnendu Chakrabarty	Test-wrapper optimisation for embedded cores in through-silicon via-based three-dimensional system on chips.	IET Comput. Digit. Tech.	2011	DBLP DOI BibTeX RDF
14	Ali Ahmadinia, Hernando Fernandez-Canque	Optimization of reconfigurable multi-core system-on-chips for multi-standard applications.	Int. J. Knowl. Based Intell. Eng. Syst.	2011	DBLP DOI BibTeX RDF
14	Shaon Yousuf, Adam Jacobs, Ann Gordon-Ross	Partially reconfigurable system-on-chips for adaptive fault tolerance.	FPT	2011	DBLP DOI BibTeX RDF
14	Abelardo Jara-Berrocal, Ann Gordon-Ross	An integrated development toolset and implementation methodology for partially reconfigurable system-on-chips.	ASAP	2011	DBLP DOI BibTeX RDF
14	Yi Ni, Wai Sum Mong, Jianwen Zhu	On virtual prototyping of embedded system-on-chips.	ASICON	2011	DBLP DOI BibTeX RDF