Search results for "tlb"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
201	Jinzhan Peng, Guei-Yuan Lueh, Gansha Wu, Xiaogang Gou, Ryan N. Rakvic	A comprehensive study of hardware/software approaches to improve TLB performance for java applications on embedded systems.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	TLB performance, Java, embedded system
169	Rupak Samanta, Jason Surprise, Rabi N. Mahapatra	Dynamic Aggregation of Virtual Addresses in TLB Using TCAM Cells.	VLSI Design	2008	DBLP DOI BibTeX RDF
169	Yen-Jen Chang, Maofeng Lan	Two New Techniques Integrated for Energy-Efficient TLB Design.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
156	Abhishek Bhattacharjee, Margaret Martonosi	Inter-core cooperative TLB for chip multiprocessors.	ASPLOS	2010	DBLP DOI BibTeX RDF	parallelism, prefetching, translation lookaside buffer
144	Yen-Jen Chang	An ultra low-power TLB design.	DATE	2006	DBLP DOI BibTeX RDF
132	Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivastava	Code Transformations for TLB Power Reduction.	VLSI Design	2009	DBLP DOI BibTeX RDF
132	Cheol Ho Park, JaeWoong Chung, Byeong Hag Seong, Yangwoo Roh, Daeyeon Park	Boosting superpage utilization with the shadow memory and the partial-subblock TLB.	ICS	2000	DBLP DOI BibTeX RDF
132	Madhusudhan Talluri, Mark D. Hill	Surpassing the TLB Performance of Superpages with Less Operating System Support.	ASPLOS	1994	DBLP DOI BibTeX RDF
123	Todd M. Austin, Gurindar S. Sohi	High-Bandwidth Address Translation for Multiple-Issue Processors.	ISCA	1996	DBLP DOI BibTeX RDF
119	Jin-Hyuck Choi, Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim	An Advanced Filtering TLB for Low Power Consumption.	SBAC-PAD	2002	DBLP DOI BibTeX RDF
107	Jung-Hoon Lee, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim	A selective filter-bank TLB system.	ISLPED	2003	DBLP DOI BibTeX RDF	performance evaluation, translation lookaside buffer, low power consumption, filtering mechanism
103	Chinnakrishnan S. Ballapuram, Kiran Puttaswamy, Gabriel H. Loh, Hsien-Hsin S. Lee	Entropy-based low power data TLB design.	CASES	2006	DBLP DOI BibTeX RDF	low-power TLB, spatial and temporal locality, entropy
98	Xiaogang Qiu, Michel Dubois 0001	Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	dynamic address translation, virtual-address caches, simulations, Multiprocessors, distributed shared memory, virtual memory
98	David Channon, David Koch	Performance Analysis of Re-configurable Partitioned TLBs.	HICSS (5)	1997	DBLP DOI BibTeX RDF	Computer Architecture, Memory Management, Partitioning Algorithm, Address Translation
95	Satoshi Yamada, Shigeru Kusakabe	Effect of context aware scheduler on TLB.	IPDPS	2008	DBLP DOI BibTeX RDF
95	Gokul B. Kandiraju, Anand Sivasubramaniam	Characterizing the d-TLB behavior of SPEC CPU2000 benchmarks.	SIGMETRICS	2002	DBLP DOI BibTeX RDF
95	Mark R. Swanson, Leigh Stoller, John B. Carter	Increasing TLB Reach Using Superpages Backed by Shadow Memory.	ISCA	1998	DBLP DOI BibTeX RDF
95	Theodore H. Romer, Wayne H. Ohlrich, Anna R. Karlin, Brian N. Bershad	Reducing TLB and Memory Overhead Using Online Superpage Promotion.	ISCA	1995	DBLP DOI BibTeX RDF
92	Dongrui Fan, Zhimin Tang, Hailin Huang, Guang R. Gao	An energy efficient TLB design methodology.	ISLPED	2005	DBLP DOI BibTeX RDF	Godson-I, embedded processor design, single-port RAM, energy efficient, TLB, low-power consumption
91	Chinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee, Milos Prvulovic	Synonymous address compaction for energy reduction in data TLB.	ISLPED	2005	DBLP DOI BibTeX RDF	low-power TLB, spatial and temporal locality, multi-porting
86	Omesh Tickoo, Hari Kannan, Vineet Chadha, Ramesh Illikkal, Ravi R. Iyer 0001, Donald Newell	qTLB: Looking Inside the Look-Aside Buffer.	HiPC	2007	DBLP DOI BibTeX RDF
83	Xiantao Zhang, Anthony X. F. Xu, Qi Li 0002, David K. Y. Yau, Sihan Qing, Huanguo Zhang	A hash-TLB approach for MMU virtualization in xen/IA64.	IPDPS	2008	DBLP DOI BibTeX RDF
83	Naohiko Shimizu, Ken Takatori	A transparent Linux super page kernel for Alpha, Sparc64 and IA32: reducing TLB misses of applications.	SIGARCH Comput. Archit. News	2003	DBLP DOI BibTeX RDF	Linux
83	Gokul B. Kandiraju, Anand Sivasubramaniam	Going the Distance for TLB Prefetching: An Application-Driven Study.	ISCA	2002	DBLP DOI BibTeX RDF	Application-driven Study, Simulation, Prefetching, Memory Hierarchy, Translation Lookaside Buffer
83	Ashley Saulsbury, Fredrik Dahlgren, Per Stenström	Recency-based TLB preloading.	ISCA	2000	DBLP DOI BibTeX RDF
82	Yukikazu Nakamoto	Operating System Supports to Enhance Fault Tolerance of Real-Time Systems.	WORDS	2003	DBLP DOI BibTeX RDF	Virtual Memory Management, Translation Look a side Buffer (TLB), Real-time Operating System, RISC Processor
78	Han-Xin Sun, Kun-Peng Yang, Yulai Zhao 0003, Dong Tong 0001, Xu Cheng 0001	CASA: A New IFU Architecture for Power-Efficient Instruction Cache and TLB Designs.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	instruction TLB, instruction fetch unit, power-efficient design, computer architecture, dynamic voltage scaling, instruction cache
74	Cristan Szmajda, Gernot Heiser	Variable Radix Page Table: A Page Table for Modern Architectures.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
74	David L. Black 0001, Richard F. Rashid, David B. Golub, Charles R. Hill, Robert V. Baron	Translation Lookaside Buffer Consistency: A Software Approach.	ASPLOS	1989	DBLP DOI BibTeX RDF	UNIX
71	Kelvin K. Lee, Samuel T. Chanson	Transient analysis of cell loss control mechanisms in ATM networks.	ICCCN	1995	DBLP DOI BibTeX RDF	cell loss control mechanisms, partial buffer sharing, cell loss control mechanism, threshold-based loss balancing, violation probability, ATM networks, transient analysis, transient analysis, TLB, network utilization, queue length distributions, PBS
70	Karthik Ganesan 0006, Deepak Panwar, Lizy K. John	Generation, Validation and Analysis of SPEC CPU2006 Simulation Points Based on Branch, Memory and TLB Characteristics.	SPEC Benchmark Workshop	2009	DBLP DOI BibTeX RDF
70	Adam Wiggins, Harvey Tuch, Volkmar Uhlig, Gernot Heiser	Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM Processor.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
70	David F. Bacon, Jyh-Herng Chow, Dz-Ching Ju, Kalyan Muthukumar, Vivek Sarkar	A compiler framework for restructuring data declarations to enhance cache and TLB effectiveness.	CASCON	1994	DBLP BibTeX RDF
70	Neungsoo Park, Bo Hong, Viktor K. Prasanna	Tiling, Block Data Layout, and Memory Hierarchy Performance.	IEEE Trans. Parallel Distributed Syst.	2003	DBLP DOI BibTeX RDF	Block data layout, TLB misses, memory hierarchy, tiling, cache misses
66	Ilya Chukhman, Peter Petrov	Context-aware TLB preloading for interference reduction in embedded multi-tasked systems.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	TLB management, real-time multi-processing
66	Hsien-Hsin S. Lee, Chinnakrishnan S. Ballapuram	Energy efficient D-TLB and data cache using semantic-aware multilateral partitioning.	ISLPED	2003	DBLP DOI BibTeX RDF	low-power TLB, multi-ported memory structures, energy optimization, low-power cache
63	Andrei Tatar, Daniël Trujillo, Cristiano Giuffrida, Herbert Bos	TLB;DR: Enhancing TLB-based Attacks with TLB Desynchronized Reverse Engineering.	USENIX Security Symposium	2022	DBLP BibTeX RDF
61	Joshua Magee, Apan Qasem	A case for compiler-driven superpage allocation.	ACM Southeast Regional Conference	2009	DBLP DOI BibTeX RDF
61	Peter Petrov, Alex Orailoglu	Virtual Page Tag Reduction for Low-power TLBs.	ICCD	2003	DBLP DOI BibTeX RDF
61	Yefim Shuf, Mauricio J. Serrano, Manish Gupta 0002, Jaswinder Pal Singh	Characterizing the memory behavior of Java workloads: a structured view and opportunities for optimizations.	SIGMETRICS/Performance	2001	DBLP DOI BibTeX RDF
58	Michael D. Adams 0001, David S. Wise	Seven at one stroke: results from a cache-oblivious paradigm for scalable matrix algorithms.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	Morton-hybrid, parallel processing, paging, quadtrees, Cholesky factorization, cache misses, TLB
58	Feihui Li, Mahmut T. Kandemir	Increasing Data TLB Resilience to Transient Errors.	ISVLSI	2005	DBLP DOI BibTeX RDF
58	Shivakumar Swaminathan, Sanjay B. Patel, James Dieffenderfer, Joel Silberman	Reducing Power Consumption during TLB Lookups in a PowerPC Embedded Processor.	ISQED	2005	DBLP DOI BibTeX RDF
58	Mahmut T. Kandemir, Ismail Kadayif, Guilin Chen	Compiler-directed code restructuring for reducing data TLB energy.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	code restructuring
57	Vincent Loechner, Benoît Meister, Philippe Clauss	Data Sequence Locality: A Generalization of Temporal Locality.	Euro-Par	2001	DBLP DOI BibTeX RDF	cache and TLB performance, parameterized polyhedra, Ehrhart polynomials, Memory hierarchy, temporal locality, loop nests
55	André Seznec	Concurrent Support of Multiple Page Sizes on a Skewed Associative TLB.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	multiple page size, skewed associativity, TLB
55	Nathan Kalyanasundharam, Nital Patwa	Simultaneous Switching Noise Considerations in the Design of a High Speed, Multiported TLB of a Server-Class Microprocessor.	ICCD	1999	DBLP DOI BibTeX RDF	multiported, supply inductance, TLB, simultaneous switching noise, decoupling capacitance
49	Vineet Chadha, Ramesh Illikkal, Ravi R. Iyer 0001, Jaideep Moses, Donald Newell, Renato J. O. Figueiredo	I/O processing in a virtualized platform: a simulation-driven approach.	VEE	2007	DBLP DOI BibTeX RDF	simulation, virtual machines, virtualization, performance model, xen
49	Victor Delaluz, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan	Reducing dTLB Energy Through Dynamic Resizing.	ICCD	2003	DBLP DOI BibTeX RDF
49	Neungsoo Park, Bo Hong, Viktor K. Prasanna	Analysis of Memory Hierarchy Performance of Block Data Layout.	ICPP	2002	DBLP DOI BibTeX RDF
49	Bryan S. Rosenburg	Low-Synchronization Translation Lookaside Buffer Consistency in Large-Scale Shared-Memory Multiprocessors.	SOSP	1989	DBLP DOI BibTeX RDF
46	Mel Gorman, Patrick Healy	Supporting superpage allocation without additional hardware support.	ISMM	2008	DBLP DOI BibTeX RDF	superpage, fragmentation, replacement policy, tlb
46	Martin Hirzel	Data layouts for object-oriented programs.	SIGMETRICS	2007	DBLP DOI BibTeX RDF	GC, cache, data placement, spatial locality, data layout, TLB, hardware performance counters, memory subsystem
46	Collin McCurdy, Alan L. Cox, Jeffrey S. Vetter	Investigating the TLB Behavior of High-end Scientific Applications on Commodity Microprocessors.	ISPASS	2008	DBLP DOI BibTeX RDF
46	Ismail Kadayif, Partho Nath, Mahmut T. Kandemir, Anand Sivasubramaniam	Reducing Data TLB Power via Compiler-Directed Address Generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
46	Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. Kandemir, Gokul B. Kandiraju, Guangyu Chen	Optimizing instruction TLB energy using software and hardware techniques.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	instruction locality, translation look-aside buffer, Power consumption, compiler optimization, cache design
46	Jack J. Dongarra, Shirley Moore, Philip Mucci, Keith Seymour, Haihang You	Accurate Cache and TLB Characterization Using Hardware Counters.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
46	Philip Machanick, Zunaid Patel	L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
46	Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. Kandemir, Gokul B. Kandiraju, Guangyu Chen	Generating physical addresses directly for saving instruction TLB energy.	MICRO	2002	DBLP DOI BibTeX RDF
46	Magnus Ekman, Per Stenström, Fredrik Dahlgren	TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors.	ISLPED	2002	DBLP DOI BibTeX RDF	virtual caches, low-power, CMP, snoop
45	Richard Uhlig, David Nagle, Timothy J. Stanley, Trevor N. Mudge, Stuart Sechrest, Richard B. Brown	Design Tradeoffs for Software-Managed TLBs.	ACM Trans. Comput. Syst.	1994	DBLP DOI BibTeX RDF	translation lookaside buffer (TLB), trap-driven simulation, hardware monitoring
42	Farid Yuli Martin Adiyatma, Dwi Joko Suroso, Panarat Cherntanomwong	TLB & WC-TLB-MM: The Improved Min-Max Algorithms for Multi Targets Indoor Localization.	IEEE Access	2023	DBLP DOI BibTeX RDF
42	Bang Di, Daokun Hu, Zhen Xie, Jianhua Sun 0002, Hao Chen 0002, Jinkui Ren, Dong Li 0001	TLB-pilot: Mitigating TLB Contention Attack on GPUs with Microarchitecture-Aware Scheduling.	ACM Trans. Archit. Code Optim.	2022	DBLP DOI BibTeX RDF
42	Andrés Rainiero Hernández Coronado, Wei-Ming Lin	Effective TLB thrashing: unveiling the true short reach of modern TLB designs.	SAC	2022	DBLP DOI BibTeX RDF
42	Jesung Kim, Jongmin Lee 0002, Soontae Kim	TLB Index-Based Tagging for Reducing Data Cache and TLB Energy Consumption.	IEEE Trans. Computers	2017	DBLP DOI BibTeX RDF
42	Amro Awad, Arkaprava Basu, Sergey Blagodurov, Yan Solihin, Gabriel H. Loh	Avoiding TLB Shootdowns Through Self-Invalidating TLB Entries.	PACT	2017	DBLP DOI BibTeX RDF
42	Jee Ho Ryoo, Nagendra Gulur, Shuang Song 0007, Lizy K. John	Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB.	ISCA	2017	DBLP DOI BibTeX RDF
42	Chang Hyun Park 0001, Taekyung Heo, Jungi Jeong, Jaehyuk Huh 0001	Hybrid TLB Coalescing: Improving TLB Translation Coverage under Diverse Fragmented Memory Allocations.	ISCA	2017	DBLP DOI BibTeX RDF
42	Carlos Villavieja, Vasileios Karakostas, Lluís Vilanova, Yoav Etsion, Alex Ramírez, Avi Mendelson, Nacho Navarro, Adrián Cristal, Osman S. Unsal	DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory.	PACT	2011	DBLP DOI BibTeX RDF
42	Byeong Hag Seong, Donggook Kim, Yangwoo Roh, Kyu Ho Park, Daeyeon Park	TLB Update-Hint: A Scalable TLB Consistency Algorithm for Cache-Coherent Non-uniform Memory Access Multiprocessors.	IEICE Trans. Inf. Syst.	2004	DBLP BibTeX RDF
41	Girish Venkatasubramanian, Renato J. O. Figueiredo, Ramesh Illikkal	On the Performance of Tagged Translation Lookaside Buffers: A Simulation-Driven Analysis.	MASCOTS	2011	DBLP DOI BibTeX RDF	hardware-managed TLB, tagged TLB, virtualization, Translation lookaside buffer, full-system simulation
37	Xiaogang Qiu, Michel Dubois 0001	The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
37	Aamer Jaleel, Bruce L. Jacob	In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs).	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Reorder-buffer (ROB), exception handlers, in-line interrupt, lock-up free, translation lookaside buffers (TLBs), performance modeling, precise interrupts
37	David Siegwart, Martin Hirzel	Improving locality with parallel hierarchical copying GC.	ISMM	2006	DBLP DOI BibTeX RDF	parallel, generational, cache locality
37	Wayne Pfeiffer	Memory Performance Model for Loops and Kernels on Power3 Processors.	IPDPS	2004	DBLP DOI BibTeX RDF
37	Xiaogang Qiu, Michel Dubois 0001	Towards Virtually-Addressed Memory Hierarchies.	HPCA	2001	DBLP DOI BibTeX RDF
37	Zhen Fang 0002, Lixin Zhang 0002, John B. Carter, Wilson C. Hsieh, Sally A. McKee	Reevaluating Online Superpage Promotion with Hardware Support.	HPCA	2001	DBLP DOI BibTeX RDF
37	Xiaogang Qiu, Michel Dubois 0001	Options for Dynamic Address Translation in COMAs.	ISCA	1998	DBLP DOI BibTeX RDF
34	Rui Min, Wen-Ben Jone, Yiming Hu	Location cache: a low-power L2 cache system.	ISLPED	2004	DBLP DOI BibTeX RDF	L1/L2 caches, data location, power, TLB, set-associative caches
34	Rui Min, Yiming Hu	Improving Performance of Large Physically Indexed Caches by Decoupling Memory Addresses from Cache Addresses.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Novel memory architectures, cache, memory systems, TLB, performance enhancement
34	Richard Uhlig, David Nagle, Trevor N. Mudge, Stuart Sechrest	Trap-driven Simulation with Tapeworm II.	ASPLOS	1994	DBLP DOI BibTeX RDF	trap-driven simulation, cache, trace-driven simulation, memory system, TLB
33		Translation Lookaside Buffer (TLB).	Encyclopedia of Database Systems	2009	DBLP DOI BibTeX RDF
33	Stefan Groesbrink, Timo Kerstan	Modular paging with dynamic TLB partitioning for embedded real-time systems.	SIES	2008	DBLP DOI BibTeX RDF
33	Ismail Kadayif, Mahmut T. Kandemir, I. Demirkiran	Compiler-Guided Code Restructuring for Improving Instruction TLB Energy Behavior.	Euro-Par	2004	DBLP DOI BibTeX RDF
33	Naila Rahman	Algorithms for Hardware Caches and TLB.	Algorithms for Memory Hierarchies	2002	DBLP DOI BibTeX RDF
33	Aamer Jaleel, Bruce L. Jacob	Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers.	HiPC	2001	DBLP DOI BibTeX RDF
33	Bruce L. Jacob, Trevor N. Mudge	A Look at Several Memory Management Units, TLB-Refill Mechanisms, and Page Table Organizations.	ASPLOS	1998	DBLP DOI BibTeX RDF
25	Ryan W. Moore, José Baiocchi, Bruce R. Childers, Jack W. Davidson, Jason Hiser	Addressing the challenges of DBT for the ARM architecture.	LCTES	2009	DBLP DOI BibTeX RDF	virtualization, dynamic binary translation, arm
25	Moon-Sang Lee, Joonwon Lee, Seungryoul Maeng	Context-aware address translation for high performance SMP cluster system.	CLUSTER	2008	DBLP DOI BibTeX RDF
25	Jaume Abella 0001, Antonio González 0001	SAMIE-LSQ: set-associative multiple-instruction entry load/store queue.	IPDPS	2006	DBLP DOI BibTeX RDF
25	Yen-Jen Chang	An Alternative Real-Time Filter Scheme to Block Buffering.	VLSI Design	2006	DBLP DOI BibTeX RDF
25	Xiangrong Zhou, Peter Petrov	Arithmetic-based address translation for energy-efficient virtual memory support in low-power, real-time embedded systems.	SBCCI	2005	DBLP DOI BibTeX RDF
25	Ismail Kadayif, Partho Nath, Mahmut T. Kandemir, Anand Sivasubramaniam	Compiler-directed physical address generation for reducing dTLB power.	ISPASS	2004	DBLP DOI BibTeX RDF
25	Danko Butorac	Talking Linux for the Blind - A CD Distribution with Speech.	ICCHP	2004	DBLP DOI BibTeX RDF
25	Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas	A Dynamically Tunable Memory Hierarchy.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	High performance microprocessors, energy and performance of on-chip caches, memory hierarchy, reconfigurable architectures
25	Adam Wiggins, Simon Winwood, Harvey Tuch, Gernot Heiser	Legba: Fast Hardware Support for Fine-Grained Protection.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
25	Ruoming Jin, Gagan Agrawal	Performance prediction for random write reductions: a case study in modeling shared memory programs.	SIGMETRICS	2002	DBLP DOI BibTeX RDF
25	Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan	Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost.	ICCD	2002	DBLP DOI BibTeX RDF
25	Michael Penner, Viktor K. Prasanna	Cache-Friendly Implementations of Transitive Closure.	IEEE PACT	2001	DBLP DOI BibTeX RDF
25	Naila Rahman, Richard Cole 0001, Rajeev Raman	Optimised Predecessor Data Structures for Internal Memory.	WAE	2001	DBLP DOI BibTeX RDF