Search results for "tool-flow"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
34	Christos P. Sotiriou	Implementing asynchronous circuits using a conventional EDA tool-flow.	DAC	2002	DBLP DOI BibTeX RDF	tool-flow, asynchronous, EDA
31	Bjorn De Sutter, Diederik Verkest, Erik Brockmeyer, Eric Delfosse, Arnout Vandecappelle, Jean-Yves Mignolet	Design and Tool Flow of Multimedia MPSoC Platforms.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Tool flow, Multimedia, Parallelization, Predictability, MPSoC
21	Brahim Al Farisi, Karel Bruneel, Harald Devos, Dirk Stroobandt	Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	parameterizable configurations, tmap, fpga, reconfigurable computing, run-time reconfiguration, srl, icap
20	Robert N. Blair, Jacques Benkoski	How Do You Select A High Quality EDA Tool Flow?.	ISQED	2000	DBLP DOI BibTeX RDF
16	Choong Soo Lee, Hyun Jong Kim	A Part Release considering Tool Scheduling and Dynamic Tool Allocation in Flexible Manufacturing Systems.	ICAS	2006	DBLP DOI BibTeX RDF
15	John Ferguson	The Glue in a Confident SoC Flow.	IWSOC	2003	DBLP DOI BibTeX RDF	manufacturing requirements, gold standard, single tool flow, design-to-silicon, designstyle independence, confident data transfer, Integration
11	Greg Stitt, Frank Vahid	Binary synthesis.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Binary synthesis, synthesis from software binaries, FPGA, hardware/software codesign, hardware/software partitioning, configurable logic, warp processors
10	Andy D. Pimentel, Todor P. Stefanov, Hristo Nikolov, Mark Thompson 0001, Simon Polstra, Ed F. Deprettere	Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study.	SAMOS	2008	DBLP DOI BibTeX RDF
9	Daniel Seita, Yufei Wang, Sarthak J. Shetty, Edward Yao Li, Zackory Erickson, David Held	ToolFlowNet: Robotic Manipulation with Tools via Predicting Tool Flow from Point Clouds.	CoRR	2022	DBLP DOI BibTeX RDF
9	Daniel Seita, Yufei Wang, Sarthak J. Shetty, Edward Yao Li, Zackory Erickson, David Held	ToolFlowNet: Robotic Manipulation with Tools via Predicting Tool Flow from Point Clouds.	CoRL	2022	DBLP BibTeX RDF
9	Heechun Park, Bon Woong Ku, Kyungwook Chang, Da Eun Shim, Sung Kyu Lim	Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs.	ISPD	2020	DBLP DOI BibTeX RDF
9	Lalitha Mohana Kalyani-Garimella, Sri Raga Sudha Garimella	Novel 3D Monotonic Characterization of Standard Cell Liberty File Attributes w.r.t ASIC Tool Flow.	MWSCAS	2019	DBLP DOI BibTeX RDF
9	Florian Fricke, André Werner 0001, Keyvan Shahin, Florian Werner 0002, Michael Hübner 0001	Automatic Tool-Flow for Mapping Applications to an Application-Specific CGRA Architecture.	IPDPS Workshops	2019	DBLP DOI BibTeX RDF
9	Khoa Dang Pham, Malte Vesper, Dirk Koch, Eddie Hung	EFCAD - An Embedded FPGA CAD Tool Flow for Enabling On-chip Self-Compilation.	FCCM	2019	DBLP DOI BibTeX RDF
9	Heechun Park, Kyungwook Chang, Bon Woong Ku, Jinwoo Kim, Edward Lee, Daehyun Kim 0002, Arjun Chaudhuri, Sanmitra Banerjee, Saibal Mukhopadhyay, Krishnendu Chakrabarty, Sung Kyu Lim	RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs.	DAC	2019	DBLP DOI BibTeX RDF
9	Lalitha Mohana Kalyani-Garimella, Sri Raga Sudha Garimella	Novel 3D Monotonic Characterization of Standard Cell Liberty File Attributes w.r.t ASIC Tool Flow.	MWSCAS	2018	DBLP DOI BibTeX RDF
9	Oluseyi A. Ayorinde, He Qi, Benton H. Calhoun	FGC: A Tool-flow for Generating and Configuring Custom FPGAs(Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
9	Jeongbin Kim 0001, Ki Tae Kim, Eui-Young Chung	CAD Tool Flow for Variation-Tolerant Non-Volatile STT-MRAM LUT based FPGA.	ICSCA	2018	DBLP DOI BibTeX RDF
9	Florian Fricke, André Werner 0001, Keyvan Shahin, Michael Hübner 0001	CGRA Tool Flow for Fast Run-Time Reconfiguration.	ARC	2018	DBLP DOI BibTeX RDF
9	Luis Andrés Cardona, Anees Ullah, Luca Sterpone, Carles Ferrer 0001	A novel tool-flow for zero-overhead cross-domain error resilient partially reconfigurable X-TMR for SRAM-based FPGAs.	J. Syst. Archit.	2017	DBLP DOI BibTeX RDF
9	Cristina Silvano, Giovanni Agosta, Jorge G. Barbosa, Andrea Bartolini, Andrea Rosario Beccari, Luca Benini, João Bispo, João M. P. Cardoso, Carlo Cavazzoni, Stefano Cherubin, Radim Cmar, Davide Gadioli, Candida Manelfi, Jan Martinovic, Ricardo Nobre, Gianluca Palermo, Martin Palkovic, Pedro Pinto 0002, Erven Rohou, Nico Sanna, Katerina Slaninová	The ANTAREX tool flow for monitoring and autotuning energy efficient HPC systems.	SAMOS	2017	DBLP DOI BibTeX RDF
9	Lekhobola J. Tsoeunyane, Simon Winberg, Michael Inggs	An IP core integration tool-flow for prototyping software-defined radios using static dataflow with access patterns.	FPT	2017	DBLP DOI BibTeX RDF
9	Florian Fricke, André Werner 0001, Michael Hübner 0001	Tool flow for automatic generation of architectures and test-cases to enable the evaluation of CGRAs in the context of HPC applications.	DASIP	2017	DBLP DOI BibTeX RDF
9	Tobias Wiersema, Arne Bockhorn, Marco Platzner	An architecture and design tool flow for embedding a virtual FPGA into a reconfigurable system-on-chip.	Comput. Electr. Eng.	2016	DBLP DOI BibTeX RDF
9	Filipp Akopyan	Design and Tool Flow of IBM's TrueNorth: an Ultra-Low Power Programmable Neurosynaptic Chip with 1 Million Neurons.	ISPD	2016	DBLP DOI BibTeX RDF
9	Tasmiat Rahman, Kristel Fobelets	Efficient tool flow for 3D photovoltaic modelling.	Comput. Phys. Commun.	2015	DBLP DOI BibTeX RDF
9	Simon Reder, Christoph Roth, Harald Bucher, Oliver Sander, Jürgen Becker 0001	Adaptive algorithm and tool flow for accelerating SystemC on many-core architectures.	Microprocess. Microsystems	2015	DBLP DOI BibTeX RDF
9	Filipp Akopyan, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John V. Arthur, Paul Merolla, Nabil Imam, Yutaka Y. Nakamura, Pallab Datta, Gi-Joon Nam, Brian Taba, Michael P. Beakes, Bernard Brezzo, Jente B. Kuang, Rajit Manohar, William P. Risk, Bryan L. Jackson, Dharmendra S. Modha	TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2015	DBLP DOI BibTeX RDF
9	Christos Papameletis, Brion L. Keller, Vivek Chickermane, Said Hamdioui, Erik Jan Marinissen	A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers.	IEEE Des. Test	2015	DBLP DOI BibTeX RDF
9	Martin Becker 0001, Sajid Mohamed, Karsten Albers, P. P. Chakrabarti 0001, Samarjit Chakraborty, Pallab Dasgupta, Soumyajit Dey, Ravindra Metta	Timing Analysis of Safety-Critical Automotive Software: The AUTOSAFE Tool Flow.	APSEC	2015	DBLP DOI BibTeX RDF
9	Jens Korinth, David de la Chevallerie, Andreas Koch 0001	An Open-Source Tool Flow for the Composition of Reconfigurable Hardware Thread Pool Architectures.	FCCM	2015	DBLP DOI BibTeX RDF
9	Christoph Roth, Simon Reder, Harald Bucher, Oliver Sander, Jürgen Becker 0001	Adaptive Algorithm and Tool Flow for Accelerating System C on Many-Core Architectures.	DSD	2014	DBLP DOI BibTeX RDF
9	Aritra Hazra, Rajdeep Mukherjee, Pallab Dasgupta, Ajit Pal, Kevin Harer, Ansuman Banerjee, Subhankar Mukherjee 0001	POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2013	DBLP DOI BibTeX RDF
9	Brahim Al Farisi, Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt	A novel tool flow for increased routing configuration similarity in multi-mode circuits.	ISVLSI	2013	DBLP DOI BibTeX RDF
9	Brahim Al Farisi, Karel Bruneel, João M. P. Cardoso, Dirk Stroobandt	An automatic tool flow for the combined implementation of multi-mode circuits.	DATE	2013	DBLP DOI BibTeX RDF
9	Kyprianos Papadimitriou, Christian Pilato, Dionisios N. Pnevmatikatos, Marco D. Santambrogio, Catalin Bogdan Ciobanu, Tim Todman, Tobias Becker, Tom Davidson, Xinyu Niu, Georgi Gaydadjiev, Wayne Luk, Dirk Stroobandt	Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration.	CSE	2012	DBLP DOI BibTeX RDF
9	Greg Stitt, Alan D. George, Herman Lam, Melissa C. Smith, Vikas Aggarwal, Gongyu Wang, Casey Reardon, Brian Holland, Seth Koehler, James Coole	An End-to-End Tool Flow for FPGA-Accelerated Scientific Computing.	IEEE Des. Test Comput.	2011	DBLP DOI BibTeX RDF
9	Neil Steiner, Aaron Wood, Hamid Shojaei, Jacob Couch, Peter Athanas, Matthew French	Torc: towards an open-source tool flow.	FPGA	2011	DBLP DOI BibTeX RDF
9	Stephanie Drzevitzky, Uwe Kastens, Marco Platzner	Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification.	Int. J. Reconfigurable Comput.	2010	DBLP DOI BibTeX RDF
9	Mariusz Grad, Christian Plessl	Woolcano: An Architecture And Tool Flow For Dynamic Instruction Set Extension On Xilinx Virtex-4 FX.	ERSA	2009	DBLP BibTeX RDF
9	Markus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf, Manfred Glesner	An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs.	FPL	2009	DBLP DOI BibTeX RDF
9	Mohammad Reza Kakoee, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Ciprian Seiculescu, Luca Benini	A floorplan-aware interactive tool flow for NoC design and synthesis.	SoCC	2009	DBLP DOI BibTeX RDF
9	Jin Guo 0001, Antonis Papanikolaou, Michele Stucchi, Kristof Croes, Zsolt Tokei, Francky Catthoor	A tool flow for predicting system level timing failures due to interconnect reliability degradation.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	system degradation, system level failures, interconnect reliability
9	Kelly Nasi, Martin Danek, Theodoros Karoubalis, Zdenek Pohl	Figaro: an automatic tool flow for designs with dynamic reconfiguration (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
9	Kelly Nasi, Martin Danek, Theodoros Karoubalis, Zdenek Pohl	Figaro - An Automatic Tool Flow for Designs with Dynamic Reconfiguration.	FPL	2005	DBLP DOI BibTeX RDF
9	Gerard J. M. Smit, Michèl A. J. Rosien, Yuanqing Guo, Paul M. Heysters	Overview of the Tool-flow for the Montium Processor Tile.	ERSA	2004	DBLP BibTeX RDF
9	Mustafa Özbayrak, Ahmet Kürsad Türker, Melek Pisman	Part and Tool Flow Management in Multi-Cell Flexible Manufacturing System.	WSC	1997	DBLP DOI BibTeX RDF
8	Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai	Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Compilers for low energy, loop buffers, VLIW processors
8	Anup Kumar Raghavan, Peter Sutton	JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs.	IPDPS	2002	DBLP DOI BibTeX RDF	JBits, FPGA design flow, Partial Bitstream, Xilinx Virtex, Partial Reconfiguration
8	Vincent John Mooney III	Path-based Edge Activation for Dynamic Run-Time Scheduling.	ISSS	1999	DBLP DOI BibTeX RDF
7	Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier	Template-Based Generation of Streaming Accelators from a High Level Presentation.	FCCM	2006	DBLP DOI BibTeX RDF
6	Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco	Event-driven gate-level simulation with GP-GPUs.	DAC	2009	DBLP DOI BibTeX RDF	gate-level simulation, general purpose graphics processing unit (GP-GPU), high-performance simulation
6	Trevor Meyerowitz, Alberto L. Sangiovanni-Vincentelli, Mirko Sauermann, Dominik Langen	Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor.	DATE	2008	DBLP DOI BibTeX RDF
6	Hristo Nikolov, Mark Thompson 0001, Todor P. Stefanov, Andy D. Pimentel, Simon Polstra, Raj Bose, Claudiu Zissulescu, Ed F. Deprettere	Daedalus: toward composable multimedia MP-SoC design.	DAC	2008	DBLP DOI BibTeX RDF	system-level design and synthesis, design space exploration
6	Andrea Marongiu, Luca Benini, Mahmut T. Kandemir	Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms.	CASES	2007	DBLP DOI BibTeX RDF	code parallelization, MPSoCs, barrier synchronization
6	Carlos Morra, M. Sackmann, Sunil Shukla, Jürgen Becker 0001, Reiner W. Hartenstein	From Equation to VHDL: Using Rewriting Logic for Automated Function Generation.	FPL	2006	DBLP DOI BibTeX RDF
6	Weifeng Xu, Ramshankar Ramanarayanan, Russell Tessier	Adaptive Fault Recovery for Networked Reconfigurable Systems.	FCCM	2003	DBLP DOI BibTeX RDF
6	Colin J. Ihrig, Rami G. Melhem, Alex K. Jones	Automated modeling and emulation of interconnect designs for many-core chip multiprocessors.	DAC	2010	DBLP DOI BibTeX RDF	simulation, interconnection network, emulation, multi-core, many-core
6	Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Yaun-Chung Hsu, Arun Kundu, Andrew A. Kennings	A technique for minimizing power during FPGA placement.	FPL	2008	DBLP DOI BibTeX RDF
6	Anish Muttreja, Anand Raghunathan, Srivaths Ravi 0001, Niraj K. Jha	Hybrid Simulation for Energy Estimation of Embedded Software.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
6	Eckard Böde, Marc Herbstritt, Holger Hermanns, Sven Johr, Thomas Peikenkamp, Reza Pulungan, Ralf Wimmer 0001, Bernd Becker 0001	Compositional Performability Evaluation for STATEMATE.	QEST	2006	DBLP DOI BibTeX RDF
6	Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid	Techniques for synthesizing binaries to an advanced register/memory structure.	FPGA	2005	DBLP DOI BibTeX RDF	smart buffers, FPGA, embedded systems, synthesis, decompilation, binaries
6	Greg Stitt, Frank Vahid	A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms.	DATE	2005	DBLP DOI BibTeX RDF
6	Jiangwei Huang, Tianzhou Chen, Minjiao Ye, Yi Lian	The Modeling for Dynamic Power Management of Embedded Systems.	ICESS	2004	DBLP DOI BibTeX RDF
6	Vasilios Kalenteridis, Haroula Pournara, Kostas Siozios, Konstantinos Tatas, George Koutroumpezis, Ilias Pappas 0001, Spiridon Nikolaidis 0001, Stilianos Siskos, D. J. Soudris, Adonios Thanailakis	An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development.	IPDPS	2004	DBLP DOI BibTeX RDF	Low Power FPGA interconnect architecture, CLB Architecture, Graphical User Interface
6	Eui-Young Chung, Luca Benini, Giovanni De Micheli, Gabriele Luculli, Marco Carilli	Value-sensitive automatic code specialization for embedded software.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
6	Armita Peymandoust, Tajana Simunic, Giovanni De Micheli	Low Power Embedded Software Optimization Using Symbolic Algebra.	DATE	2002	DBLP DOI BibTeX RDF
6	Rafi Levy, David T. Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov	ClariNet: a noise analysis tool for deep submicron design.	DAC	2000	DBLP DOI BibTeX RDF
4	Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003	Intel® atomTM processor core made FPGA-synthesizable.	FPGA	2009	DBLP DOI BibTeX RDF	intel atom, synthesizable core, fpga, emulator
4	George Kiokes, Nikolaos K. Uzunoglu	Development of a simulation Environment for Vehicular communications, implementation of FEC coding chain in Xilinx FPGA based on IEEE 802.11p standard.	WOWMOM	2009	DBLP DOI BibTeX RDF
4	Cheoljoo Jeong, Steven M. Nowick	Technology Mapping and Cell Merger for Asynchronous Threshold Networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
4	Seda Ogrenci Memik, Nikolaos Bellas, Somsubhra Mondal	Presynthesis Area Estimation of Reconfigurable Streaming Accelerators.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
4	Michael A. Gora, Eric Simpson, Patrick Schaumont	Intellectual Property Protection for Embedded Sensor Nodes.	SAMOS	2008	DBLP DOI BibTeX RDF
4	Daniel Kästner, Reinhard Wilhelm, Reinhold Heckmann, Marc Schlickling, Markus Pister 0002, Marek Jersak, Kai Richter 0001, Christian Ferdinand	Timing Validation of Automotive Software.	ISoLA	2008	DBLP DOI BibTeX RDF
4	Shuming Chen, Xiangyuan Liu	A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs.	NOCS	2007	DBLP DOI BibTeX RDF	differential-signaling, insertion methodology, on-chip interconnects, low-swing
4	Sjoerd Meijer, Bart Kienhuis, Johan Walters, David Snuijf	Automatic partitioning and mapping of stream-based applications onto the Intel IXP Network processor.	SCOPES	2007	DBLP DOI BibTeX RDF
4	Heiner Giefers, Marco Platzner	A Many-core Implementation based on the Reconfigurable Mesh Model.	FPL	2007	DBLP DOI BibTeX RDF
4	Colin J. Ihrig, Justin Stander, Alex K. Jones	Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions.	IPDPS	2007	DBLP DOI BibTeX RDF
4	Frank Bouwens, Mladen Berekovic, Andreas Kanstein, Georgi Gaydadjiev	Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array.	ARC	2007	DBLP DOI BibTeX RDF
4	Carlos Morra	Configware Design Space Exploration Using Rewriting Logic.	FPL	2006	DBLP DOI BibTeX RDF
4	Klaus Danne, Roland Mühlenbernd, Marco Platzner	Executing Hardware Tasks on Dynamically Reconfigurable Devices Under Real-Time Conditions.	FPL	2006	DBLP DOI BibTeX RDF
4	Patrick Lysaght, Brandon Blodget, Jeff Mason, Jay Young, Brendan Bridgford	Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
4	Miroslav N. Velev	Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction.	ISQED	2006	DBLP DOI BibTeX RDF
4	Konrad J. Kulikowski, Alexander B. Smirnov, Alexander Taubin	Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks.	CHES	2006	DBLP DOI BibTeX RDF
4	Robert B. Reese, Mitchell A. Thornton, Cherrice Traver	A Coarse-Grain Phased Logic CPU.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	asynchronous, pipelined processor, Automatic synthesis, self-timed, micropipelines
4	Christian Sauer 0001, Matthias Gries, Sören Sonntag	Modular Reference Implementation of an IP-DSLAM.	ISCC	2005	DBLP DOI BibTeX RDF
4	Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai	Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors.	ESTIMedia	2005	DBLP DOI BibTeX RDF
4	Kazutoshi Wakabayashi	System LSI design with C-based behavioral synthesis and verification.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
4	Christian Plessl, Marco Platzner	Zippy - A coarse-grained reconfigurable array with support for hardware virtualization.	ASAP	2005	DBLP DOI BibTeX RDF
4	Christian Sauer 0001, Matthias Gries, Sören Sonntag, Dietmar Toelle, Bo Wu, Rudi Knorr	Trends in Access Networks and their Implementation in DSLAMs.	LCN	2005	DBLP DOI BibTeX RDF
4	Prosenjit Chatterjee	Streamline verification process with formal property verification to meet highly compressed design cycle.	DAC	2005	DBLP DOI BibTeX RDF	formal verification
4	Anish Muttreja, Anand Raghunathan, Srivaths Ravi 0001, Niraj K. Jha	Hybrid simulation for embedded software energy estimation.	DAC	2005	DBLP DOI BibTeX RDF	energy macromodels, embedded software, pointers analysis, energy estimation, hybrid simulation
4	Kelvin Ng, Alan J. Hu, Jin Yang	Generating Monitor Circuits for Simulation-Friendly GSTE Assertion Graphs.	ICCD	2004	DBLP DOI BibTeX RDF
4	Christian Plessl, Marco Platzner	Instance-Specific Accelerators for Minimum Covering.	J. Supercomput.	2003	DBLP DOI BibTeX RDF	instance-specific acceleration, minimum covering, reconfigurable computing
4	Armita Peymandoust, Tajana Simunic, Giovanni De Micheli	Complex instruction and software library mapping for embedded software using symbolic algebra.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
4	Miroslav N. Velev	Collection of High-Level Microprocessor Bugs from Formal Verification of Pipelined and Superscalar Designs.	ITC	2003	DBLP DOI BibTeX RDF
4	Francesco Papariello, Gabriele Luculli	Optimization of a Retargetable Functional Simulator for Embedded Processors.	ECBS	2002	DBLP DOI BibTeX RDF	retargetable ISS, platform design, system-on-chip, embedded processors, system-level design
4	Kolja Sulimma, Wolfgang Kunz, Ingmar Neumann, Lukas P. P. P. van Ginneken	Improving Placement under the Constant Delay Model.	DATE	2002	DBLP DOI BibTeX RDF
4	Kee Sup Kim, Rathish Jayabharathi, Craig Carstens	SpeedGrade: An RTL Path Delay Fault Simulator.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
4	Chris Feige, Jan Ten Pierick, Clemens Wouters, Ronald J. W. T. Tangelder, Hans G. Kerkhoff	Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	bus-transfer, core reuse, test protocol, TIC, TTM, vector transfer, design-for-testability, ATPG, scan-test, AMBA