Search results for "wafer-probe"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
157	Soumendu Bhattacharya, Abhijit Chatterjee	Optimized wafer-probe and assembled package test design for analog circuits.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Assembled package, co-optimization, test cost minimization, test generation and co-optimization, wafer-probe, simulation, test, prototype, analog and mixed-signal test
123	Soumendu Bhattacharya, Abhijit Chatterjee	High Coverage Analog Wafer-Probe Test Design and Co-optimization with Assembled-Package Test to Minimize Overall Test Cost.	VTS	2003	DBLP DOI BibTeX RDF
83	Ganesh Srinivasan, Friedrich Taenzler, Abhijit Chatterjee	Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	wafer probe test, test yield, loopback test, DFT, RF test, low-cost test
75	Thomas S. Barnett, Adit D. Singh, Victor P. Nelson	Extending integrated-circuit yield-models to estimate early-life reliability.	IEEE Trans. Reliab.	2003	DBLP DOI BibTeX RDF
73	Sudarshan Bahukudumbi, Krishnendu Chakrabarty	Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
73	Sudarshan Bahukudumbi, Krishnendu Chakrabarty	Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs.	VLSI Design	2007	DBLP DOI BibTeX RDF
59	Thomas S. Barnett, Adit D. Singh, Victor P. Nelson	Yield-Reliability Modeling for Fault Tolerant Integrated Circuits.	DFT	2001	DBLP DOI BibTeX RDF	infant mortality, negative binomial distribution, clustering, reliability, redundancy, yield, defects, defect tolerance, burn-in
58	Rajiv Pandey, Dan Higgins	probe card-a solution for at-speed, high density, wafer probing.	ITC	1998	DBLP DOI BibTeX RDF
50	Soumendu Bhattacharya, Abhijit Chatterjee	Constrained Specification-Based Test Stimulus Generation for Analog Circuits Using Nonlinear Performance Prediction Models.	DELTA	2002	DBLP DOI BibTeX RDF	Wafer-probe Test, Assembled Package Test, Multivariate Adaptive Regression Splines, Genetic Algorithm
50	Karim Arabi, Bozena Kaminska	Oscillation-test strategy for analog and mixed-signal integrated circuits.	VTS	1996	DBLP DOI BibTeX RDF	circuit oscillations, oscillation test strategy, analog ICs, low-cost test method, oscillation frequency deviation, wafer-probe testing, final production testing, ASIC testing, integrated circuit testing, operational amplifiers, analogue integrated circuits, mixed analogue-digital integrated circuits, production testing, analogue-digital conversion, mixed-signal ICs
45	Thomas S. Barnett, Adit D. Singh	Relating Yield Models to Burn-In Fall-Out in Time.	ITC	2003	DBLP DOI BibTeX RDF
41	Tsung-Che Chiang, Yi-Shiuan Shen, Li-Chen Fu	Adaptive Lot/equipment Matching Strategy and GA based Approach for Optimized Dispatching and Scheduling in a Wafer Probe Center.	ICRA	2004	DBLP DOI BibTeX RDF
35	Chris Sellathamby, Md. Mahbub Reja, Lin Fu, Brenda Bai, Edwin Walter Reid, Steven Slupsky, Igor M. Filanovsky, Kris Iniewski	Noncontact wafer probe using wireless probe cards.	ITC	2005	DBLP DOI BibTeX RDF
34	Yu-Chun Dawn, Jen-Chieh Yeh, Cheng-Wen Wu, Chia-Ching Wang, Yung-Chen Lin, Chao-Hsun Chen	Flash Memory Die Sort by a Sample Classification Method.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	die sort, test flow, wafer probe, flash memory, memory testing
34	Larry Gilg	Known Good Die.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	known good die, KGD, chip scale (size) package, multi-chip module (MCM), wafer probe, membrane probe card, buckling beam probe card, KGD carrier, CSP, burn-in
33	Thomas S. Barnett, Adit D. Singh, Matt Grady, Kathleen G. Purdy	Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction.	VTS	2002	DBLP DOI BibTeX RDF
33	Zhihua Wang, Georges G. E. Gielen, Willy M. C. Sansen	Probabilistic fault detection and the selection of measurements for analog integrated circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
30	Ron Ross, Keith McCasland	Early Detection of Design Sensitivities that Cause Yield Loss for New Products.	ISQED	2001	DBLP DOI BibTeX RDF
26	A. M. Majid, David C. Keezer, J. V. Karia	A 5 Gbps Wafer-Level Tester.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
26	Paul Okino	Test Time Impact of Redundancy Repair in Embedded Flash Memory.	ITC	2002	DBLP DOI BibTeX RDF
24	Junhui Li, Hailong Liao, Dasong Ge, Can Zhou, Chengdi Xiao, Qing Tian, Wenhui Zhu	An Electromechanical Model and Simulation for Test Process of the Wafer Probe.	IEEE Trans. Ind. Electron.	2017	DBLP DOI BibTeX RDF
24	Eleonora Franchi Scarselli, Luca Perilli, Luca Perugini, Roberto Canegallo	A 40 nm CMOS I/O Pad Design With Embedded Capacitive Coupling Receiver for Non-Contact Wafer Probe Test.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
24	Abdelhatif El Fellahi, Kamel Haddadi, Jaouad Marzouk, Steve Arscott, Christophe Boyaval, Tuami Lasri, Gilles Dambrine	On-wafer probe station for microwave metrology at the nanoscale.	I2MTC	2015	DBLP DOI BibTeX RDF
24	Dragoljub Gagi Drmanac, Nik Sumikawa, LeRoy Winemberg, Li-C. Wang, Magdy S. Abadir	Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits.	DATE	2011	DBLP DOI BibTeX RDF
24	Dragoljub Gagi Drmanac, Michael Laisne	Wafer probe test cost reduction of an RF/A device by automatic testset minimization - A case study.	ITC	2011	DBLP DOI BibTeX RDF
24	Chih-Hsiung Wang	Determining the optimal probing lot size for the wafer probe operation in semiconductor manufacturing.	Eur. J. Oper. Res.	2009	DBLP DOI BibTeX RDF
24	D. S. Liu, M. K. Shih, W. H. Huang	Measurement and analysis of contact resistance in wafer probe testing.	Microelectron. Reliab.	2007	DBLP DOI BibTeX RDF
24	William R. Mann, Frederick L. Taber, Philip W. Seitzer, Jerry J. Broz	The Leading Edge of Production Wafer Probe Test Technology.	ITC	2004	DBLP DOI BibTeX RDF
24	Shun-Yu Lin, Li-Chen Fu, Tsung-Che Chiang, Yi-Shiuan Shen	Colored timed petri-net and GA based approach to modeling and scheduling for wafer probe center.	ICRA	2003	DBLP DOI BibTeX RDF
24	Gregory W. Papadeas, David Gauthier	An On-Line Data Collection and Analysis System for VLSI Devices at Wafer Probe and Final Test.	ITC	1994	DBLP DOI BibTeX RDF
24	Adit D. Singh, C. Mani Krishna 0001	On Optimizing Wafer-Probe Testing for Product Quality Using Die-Yield Prediction.	ITC	1991	DBLP DOI BibTeX RDF
24	Ming-Feng Chang, Weiping Shi, W. Kent Fuchs	Optimal wafer probe testing and diagnosis of k-out-of-n structures.	ICCAD	1989	DBLP DOI BibTeX RDF
24	Norman Nadeau, Sylvie Perreault	An Analysis of Tungsten Probes' Effect on Yield in a Production Wafer Probe Environment.	ITC	1989	DBLP DOI BibTeX RDF
16	Kazuhiko Miki, David Boerstler, Eskinder Hailu, Jieming Qi, Sarah Pettengill, Yuichi Goto	A new test and characterization scheme for 10+ GHz low jitter wide band PLL.	ASP-DAC	2006	DBLP DOI BibTeX RDF
16	Minsu Choi, Noh-Jin Park, K. M. George, Byoungjae Jin, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi	Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems.	NCA	2003	DBLP DOI BibTeX RDF	Built-in-self-repair (BISR), Field Reconfiguration, HW/SW Co-reliability, Reliability Assurance, Reliability, High performance computing, Yield, Massively parallel computing, Fault-tolerant memory, Modular Redundancy
16	Thomas S. Barnett, Adit D. Singh, Victor P. Nelson	Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability Model.	VTS	2001	DBLP DOI BibTeX RDF
16	Zao Yang, Kwang-Ting Cheng, King L. Tai	A New Bare Die Test Methodology.	VTS	1999	DBLP DOI BibTeX RDF
16	Shashank K. Mehta, Sharad C. Seth	Empirical Computation of Reject Ratio in VLSI Testing.	VLSI Design	1999	DBLP DOI BibTeX RDF
16	Frederick L. Taber	An introduction to area array probing.	ITC	1998	DBLP DOI BibTeX RDF
16	Karim Arabi, Bozena Kaminska	Testing analog and mixed-signal integrated circuits using oscillation-test method.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
16	Georges G. E. Gielen, Zhihua Wang, Willy M. C. Sansen	Fault detection and input stimulus determination for the testing of analog integrated circuits based on power-supply current monitoring.	ICCAD	1994	DBLP DOI BibTeX RDF
16	Andrew J. Bishop, André Ivanov	On the Testability of CMOS Feedback Amplifiers.	DFT	1994	DBLP DOI BibTeX RDF
16	Linda S. Milor, V. Visvanathan	Detection of catastrophic faults in analog integrated circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF