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Found 4641 publication records. Showing 4639 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
95Sunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli SPFD-based wire removal in standard-cell and network-of-PLA circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
89Chung-Ping Chen, D. F. Wong 0001 Optimal Wire-Sizing Function with Fringing Capacitance Consideration. Search on Bibsonomy DAC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
86Hongbo Zhang 0001, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng Wire shaping is practical. Search on Bibsonomy ISPD The full citation details ... 2009 DBLP  DOI  BibTeX  RDF manufacturing for design, wire tapering, interconnect, opc, power minimization
77Jason Cong, David Zhigang Pan Wire width planning for interconnect performance optimization. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
77Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay Interconnect synthesis without wire tapering. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
77Chris C. N. Chu, Martin D. F. Wong A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
77Zhong-Zhen Wu, Shih-Chieh Chang Multiple wire reconnections based on implication flow graph. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF global flow optimization (GFO), implication flow graph (IFG), mandatory assignment, multiple wire reconnection, redundant wire, Automatic test pattern generation (ATPG)
74Chris C. N. Chu, D. F. Wong 0001 A new approach to simultaneous buffer insertion and wire sizing. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF interconnect delay minimization, interconnect area minimization, convex quadratic programming, buffer insertion, wire sizing
73Paul M. Antoszczyszyn, John M. Hannah, Peter M. Grant A Comparison of Detailed Automatic Wire-Frame Fitting Methods. Search on Bibsonomy ICIP (1) The full citation details ... 1997 DBLP  DOI  BibTeX  RDF detailed automatic wire-frame fitting methods, semantic wire-frame fitting methods, extremely low bit-rate model-based moving image communication systems, lips, nose, transmitted scene, facial code-book, Candide wire-frame model, videophone scene, head-and-shoulders, MIT facial data-base, reconstruction, eyes, facial features, videotelephony
68Jason Cong, Lei He 0001, Cheng-Kok Koh, David Zhigang Pan Global interconnect sizing and spacing with consideration of coupling capacitance. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF GISS solutions, asymmetric wire sizing, delay reduction, fringing capacitances, global interconnect sizing and spacing, global wire sizing, interconnect delay minimization, multiple nets, optimal wire sizing, spacing solution, symmetric effective fringing properties, VLSI, coupling capacitance
68Qinghua Liu, Bo Hu 0006, Malgorzata Marek-Sadowska Wire length prediction in constraint driven placement. Search on Bibsonomy SLIP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF wire length prediction, clustering
65Theo van Walsum, Shirley A. M. Baert, Wiro J. Niessen Guide wire reconstruction and visualization in 3DRA using monoplane fluoroscopic imaging. Search on Bibsonomy IEEE Trans. Medical Imaging The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
65Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks. Search on Bibsonomy ICCD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
65Chung-Ping Chen, Hai Zhou 0001, D. F. Wong 0001 Optimal non-uniform wire-sizing under the Elmore delay model. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Elmore delay model, IBM RS/6000 workstation, NWSA-db, NWSA-md, NWSA-wd algorithm, general routing trees, maximum sink delay, minimization objectives, optimal nonuniform wire sizing, routing-tree problem, sink-delay bounds, total area, total weighted sink-delays, wire-sizing formula, circuit analysis computing, Lagrangian relaxation
65S. Sakurai, Takafumi Aoki, Tatsuo Higuchi 0001 Wire-Free Computing Circuits Using Optical Wave-Casting. Search on Bibsonomy ISMVL The full citation details ... 1995 DBLP  DOI  BibTeX  RDF wire-free computing circuits, optical wave-casting, interconnection problems, information carriers, wire-free logic circuits, fully parallel visual processing system, parallel processing, parallel processing, multiprocessor interconnection networks, logic circuits
65Rajat Kumar Pal, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal Computing area and wire length efficient routes for channels. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF area efficient routes, wire length efficient routes, total wire length reduction, multilayer routing solutions, computational complexity, VLSI, NP-hard, polynomial time algorithms, network routing, circuit layout CAD, minimisation, VLSI layout, integrated circuit layout, channel routing
62Ki-Jin Kim, Kwang-Ho Ahn, T. H. Lim Low Phase Noise Bond Wire VCO for DVB-H. Search on Bibsonomy DELTA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF bond wire, low phase noise, DVB-H
62Narender Hanchate, Nagarajan Ranganathan A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Game theory, transmission lines, crosstalk noise, interconnect models, wire sizing, interconnect delay
60Dongsheng Wang 0012, Ping Zhang 0001, Chung-Kuan Cheng, Arunabha Sen A Performance-Driven I/O Pin Routing Algorithm. Search on Bibsonomy ASP-DAC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
59Wen-Ting Wu, Jyh-Cheng Chen, Kai-Hsiu Chen, Kuo-Pao Fan Design and implementation of WIRE Diameter. Search on Bibsonomy ITRE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
59Chris C. N. Chu, D. F. Wong 0001 Greedy wire-sizing is linear time. Search on Bibsonomy ISPD The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
58Toshiyuki Hama, Hiroaki Etoh Curvilinear detailed routing with simultaneous wire-spreading and wire-fattening. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
56Tan Yan, Hiroshi Murata Fast wire length estimation by net bundling for block placement. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF net bundling, wire length estimation, lookup table
55Ronald I. Greenberg The Fat-Pyramid and Universal Parallel Computation Independent of Wire Delay. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF fat pyramid, universal parallel computation, wire delay, processor size, unit wire delay, routing networks, simulation, parallel computation, parallel architectures, multiprocessor interconnection networks, universality, fat-tree, wire length
53Narender Hanchate, Nagarajan Ranganathan A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
53Jin-Tai Yan, Bo-Yi Chiang, Shi-Qin Huang Width and Timing-Constrained Wire Sizing for Critical Area Minimization. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
53Qinghua Liu, Bo Hu 0006, Malgorzata Marek-Sadowska Individual wire-length prediction with application to timing-driven placement. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
53Charles J. Alpert, Anirudh Devgan, Stephen T. Quay Is wire tapering worthwhile? Search on Bibsonomy ICCAD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
53Chris C. N. Chu, D. F. Wong 0001 A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Simultaneous buffer and wire sizing, buffer sizing, interconnect optimization, wire sizing
51Zhuo Li 0001, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia Fast interconnect synthesis with layer assignment. Search on Bibsonomy ISPD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF buffer insertion, wire sizing, layer assignment, interconnect synthesis
51Krishnan Sundaresan, Nihar R. Mahapatra Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Bus Energy, Self Heating, Wire Permutation, Optimization, Interconnect, Layout, Temperature, On-Chip Bus
51Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry. Search on Bibsonomy SLIP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF wire-length distribution model, routing, interconnect, rent
51Hye Won Pyun 3D Game Engine for Real-Time Facial Animation. Search on Bibsonomy Australian Conference on Artificial Intelligence The full citation details ... 2005 DBLP  DOI  BibTeX  RDF multiple face models, wire deformation, local deformation, Real-time facial animation
50Seokjin Lee, Hua Xiang 0001, D. F. Wong 0001, Richard Y. Sun Wire type assignment for FPGA routing. Search on Bibsonomy FPGA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF min-cost flow algorithm, wire type assignment, FPGA routing
50Dirk Stroobandt Multi-terminal nets do change conventional wire length distribution models. Search on Bibsonomy SLIP The full citation details ... 2001 DBLP  DOI  BibTeX  RDF multi-terminal nets, wire length estimation, Rent's rule
50Youxin Gao, D. F. Wong 0001 Optimal shape function for a bi-directional wire under Elmore delay model. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Bi-directional wire, Optimal shape, Elmore Delay
50Takumi Okamoto, Jason Cong Buffered Steiner tree construction with wire sizing for interconnect layout optimization. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Steiner Tree, Buffer Insertion, Interconnect Optimization, Wire Sizing
48Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano Three-Dimensional Layout of On-Chip Tree-Based Networks. Search on Bibsonomy ISPAN The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Fat H-Tree, Network-on-Chip, Fat Tree, 3-D IC
48Brock J. LaMeres, Sunil P. Khatri Broadband Impedance Matching for Inductive Interconnect in VLSI Packages. Search on Bibsonomy ICCD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
48Noha H. Mahmoud, Maged Ghoneima, Yehea I. Ismail Physical limitations on the bit-rate of on-chip interconnects. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF damping factor, delay, interconnects, bit-rate
47Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer Timing-aware power-optimal ordering of signals. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Wire ordering, wire spacing, power optimization, interconnect optimization
47Yingbin Liang, Gerhard Kramer, H. Vincent Poor, Shlomo Shamai Recent results on compound wire-tap channels. Search on Bibsonomy PIMRC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
47Zhuo Li 0001, Nancy Ying Zhou, Weiping Shi Wire Sizing for Non-Tree Topology. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
47Michael Armbruster, Erik Zimmer, Matthias Lehmann, Reinhard Reichel, E. Sieglin, Gernot Spiegelberg, Armin Sulzmann Affordable X-By-Wire technology based on an innovative, scalable E/E platform-concept. Search on Bibsonomy VTC Spring The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
47Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee Timing-constrained yield-driven wire sizing for critical area minimization. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
47T. N. Vijaykumar, Zeshan Chishti Wire Delay is Not a Problem for SMT (In the Near Future). Search on Bibsonomy ISCA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
47Shirley A. M. Baert, Wiro J. Niessen 2D Guide Wire Tracking during Endovascular Interventions. Search on Bibsonomy MICCAI (2) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
47Shih-Chieh Chang, Zhong-Zhen Wu Theorems and extensions of single wire replacement. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
47Sotiris Malassiotis, Michael G. Strintzis Optimal biorthogonal wavelet decomposition of wire-frame meshes using box splines, and its application to the hierarchical coding of 3-D surfaces. Search on Bibsonomy IEEE Trans. Image Process. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
47Susanne Braun, Marcus Trapp, Claudia Nass, Matthias Gerbershagen, Stefan Schweitzer, Rodrigo Falcão, Matthias Naab, Markus Schweitzer, Torsten Kreutzer, Nikolaus Wire Insights collaboration space: a team collaboration app for the design of data-driven services. Search on Bibsonomy MoDELS (Companion) The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
47Shekhar Borkar, Robert Cohn, George W. Cox, Thomas R. Gross, H. T. Kung 0001, Monica Lam 0001, Margie Levine, Brian Moore 0004, Wire Moore, Craig Peterson, Jim Susman, Jim Sutton, John Urbanski, Jon A. Webb Supporting Systolic and Memory Communciation in iWarp. Search on Bibsonomy ISCA The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
45Hae Won Byun Multimedia Authoring Tool for Real-Time Facial Animation. Search on Bibsonomy MCAM The full citation details ... 2007 DBLP  DOI  BibTeX  RDF multiple face models, wire deformation, local deformation, real-time facial animation
45Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani How does partitioning matter for 3D floorplanning? Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF partitioning, floorplanning, 3D IC, wire length
44Kuang-Yao Lee, Shing-Tung Lin, Ting-Chi Wang Redundant via insertion with wire bending. Search on Bibsonomy ISPD The full citation details ... 2009 DBLP  DOI  BibTeX  RDF redundant via, wire bending, integer linear program
44Shuhei Amakawa, Takumi Uezono, Takashi Sato, Kenichi Okada, Kazuya Masu Adaptable wire-length distribution with tunable occupation probability. Search on Bibsonomy SLIP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF wire-length distribution, rent's rule
44Peng Liu 0024, Dingsheng Liu, Fang Huang 0001 MTF Measurement Based on Interactive Live-Wire Edge Extraction. Search on Bibsonomy International Conference on Computational Science (2) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF MTF measurement, interactive Live-wire edge extraction, sharp edge
44Dong Gun Kam, Joungho Kim, Jiheon Yu, Ho Choi, Kicheol Bae, Choonheung Lee Packaging a 40-Gbps Serial Link Using a Wire-Bonded Plastic Ball Grid Array. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF wire bonded plastic ball grid array, WB-PBGA, 40 Gb/s Serial Link, chip-to-chip serial link, SiP, System-in-Package
44Qinghua Liu, Malgorzata Marek-Sadowska Wire length prediction-based technology mapping and fanout optimization. Search on Bibsonomy ISPD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF prediction, congestion, wire length
44Young-Su Kwon, Payam Lajevardi, Anantha P. Chandrakasan, Frank Honoré, Donald E. Troxel A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool. Search on Bibsonomy SLIP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF 3-D FPGA, wire resource prediction
44Brian Stephen Smith, Sung Kyu Lim QCA channel routing with wire crossing minimization. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF QCA channel routing, weighted minimum feedback edge set, wire crossing minimization
44Vidyasagar Nookala, Sachin S. Sapatnekar A method for correcting the functionality of a wire-pipelined circuit. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF synchronous design, wire pipelining
44Muzammil Iqbal, Ahmed Sharkawy, Usman Hameed, Phillip Christie Stochastic wire length sampling for cycle time estimation. Search on Bibsonomy SLIP The full citation details ... 2002 DBLP  DOI  BibTeX  RDF cycle time estimates, wire sampling, performance modeling, physical design
44Chris C. N. Chu, D. F. Wong 0001 Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF buffer insertion, buffer sizing, closed form solution, interconnect optimization, wire sizing
42Nemanja Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz, Dean Copsey, Frederic T. Chong, Isaac L. Chuang, Mark Oskin Datapath and control for quantum wires. Search on Bibsonomy ACM Trans. Archit. Code Optim. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Architecture, Control, Layout
42Stephen E. Krufka, Phillip Christie Terminal optimization analysis for functional block re-use. Search on Bibsonomy SLIP The full citation details ... 2002 DBLP  DOI  BibTeX  RDF optimization, SoC, interconnect, Rent's rule
41Markus Krug 0004, Anton V. Schedl New demands for invehicle networks. Search on Bibsonomy EUROMICRO The full citation details ... 1997 DBLP  DOI  BibTeX  RDF in-vehicle communication networks, brake-by-wire system, steer-by-wire system, fault-tolerant communication systems, safety-critical applications, automotive electronics
41Hitoshi Kino, Toshiaki Yahiro, Fumiaki Takemura, Tetsuya Morizono Robust PD Control Using Adaptive Compensation for Completely Restrained Parallel-Wire Driven Robots: Translational Systems Using the Minimum Number of Wires Under Zero-Gravity Condition. Search on Bibsonomy IEEE Trans. Robotics The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
41Min Ni, Seda Ogrenci Memik Self-heating-aware optimal wire sizing under Elmore delay model. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
41Minsik Cho, Hua Xiang 0001, Ruchir Puri, David Z. Pan TROY: Track Router with Yield-driven Wire Planning. Search on Bibsonomy DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
41Qinghua Liu, Malgorzata Marek-Sadowska Semi-Individual Wire-Length Prediction With Application to Logic Synthesis. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
41Minsik Cho, David Z. Pan, Hua Xiang 0001, Ruchir Puri Wire density driven global routing for CMP variation and timing. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF performance, VLSI, manufacturability, global routing
41S. P. Shang, Xiaodong Hu 0001, Tong Jing Average lengths of wire routing under M-architecture and X-architecture. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
41Shirley A. M. Baert, Graeme P. Penney, Theo van Walsum, Wiro J. Niessen Precalibration Versus 2D-3D Registration for 3D Guide Wire Display in Endovascular Interventions. Search on Bibsonomy MICCAI (2) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
41Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje An analysis of the wire-load model uncertainty problem. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
41Harshit K. Shah, Pun H. Shiu, Brian Bell, Mamie Aldredge, Namarata Sopory, Jeff Davis Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects. Search on Bibsonomy ICCAD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
41Song-Ra Pan, Yao-Wen Chang Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation. Search on Bibsonomy ICCD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
41Youxin Gao, D. F. Wong 0001 Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model. Search on Bibsonomy ASP-DAC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
41John P. Fishburn Shaping a VLSI wire to minimize Elmore delay. Search on Bibsonomy ED&TC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
41Charles J. Alpert, Anirudh Devgan Wire Segmenting for Improved Buffer Insertion. Search on Bibsonomy DAC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
41Penny J. Davies, Dugald B. Duncan Time-marching numerical schemes for the electric field integral equation on a straight thin wire. Search on Bibsonomy Adv. Comput. Math. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF AMS(MOS) subject classification 65M10, 65M25, 78A45, 65R20
39Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif Congestion-driven codesign of power and signal networks. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF signal routing, wire congestion, codesign, power grid noise
39Jin-Tai Yan A simple yet effective genetic approach for the orientation assignment on cell-based layout. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF genetic approach, orientation assignment, cell-based layout, total wire length minimisation, placement phase, routing area reduction, orientation states, vertical orientation bit, horizontal orientation bit, genetic algorithms, VLSI, VLSI design, network routing, circuit layout CAD, integrated circuit layout
38Fanzhi Kong, Yizhong Wang Study on the Fast Matching Location Algorithm Based on Feature Points for Wire Bonding. Search on Bibsonomy ISIP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF wire bonding, feature points matching, SIFT, PRS
38Rupak Samanta, Jiang Hu, Peng Li 0001 Discrete buffer and wire sizing for link-based non-tree clock networks. Search on Bibsonomy ISPD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF non-tree, buffer, clock, wire, svm
38Takahiro Endo, Yuki Kawachi, Haruhisa Kawasaki, Tetsuya Mouri FPGA-Based Control for the Wire-Saving of Five-Fingered Haptic Interface. Search on Bibsonomy EuroHaptics The full citation details ... 2008 DBLP  DOI  BibTeX  RDF wire-saving control system, FPGA, Haptic interface
38Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli Early wire characterization for predictable network-on-chip global interconnects. Search on Bibsonomy SLIP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF early wire characterization, design methodology, NoCs, global interconnects
38Naim Bajçinca, Rui Cortesão, Markus Hauschild Robust Control for Steer-by-Wire Vehicles. Search on Bibsonomy Auton. Robots The full citation details ... 2005 DBLP  DOI  BibTeX  RDF steer-by-wire, inverse disturbance observer, active observer, robust control, force control, model-matching, robustness analysis
38Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu Wire Length Distribution Model Considering Core Utilization for System on Chip. Search on Bibsonomy ISVLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Wire Length Distribution, core utilization, layout-area allocation, SoC
38Mario R. Casu, Luca Macchiarulo Floorplan assisted data rate enhancement through wire pipelining: a real assessment. Search on Bibsonomy ISPD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF through-put, systems-on-chip, floorplanning, wire pipelining
38Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation. Search on Bibsonomy ISPD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF yield, buffering, design for manufacturing, wire sizing, chemical mechanical polishing (CMP)
38Hua Xiang 0001, I-Min Liu, Martin D. F. Wong Wire Planning with Bounded Over-the-Block Wires. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF over-the-block, wire planning, routing
38Qinghua Liu, Malgorzata Marek-Sadowska Pre-layout wire length and congestion estimation. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF prediction, congestion, wire length
38Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time. Search on Bibsonomy ISPD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF ?-optimal, incremental refinement, pseudo-polynomial, clock tree, wire-sizing, zero-skew
38Greg Eisenhauer, Fabián E. Bustamante, Karsten Schwan Native Data Representation: An Efficient Wire Format for High-Performance Distributed Computing. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF wire format, communication, distributed computing, High-performance
36Minsik Cho, Hua Xiang 0001, Ruchir Puri, David Z. Pan Track Routing and Optimization for Yield. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Tao Luo 0002, David Z. Pan DPlace2.0: A stable and efficient analytical placement based on diffusion. Search on Bibsonomy ASP-DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Ling Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
36Shaojun Wei, Sheqin Dong, Xianlong Hong, Youliang Wu On handling the fixed-outline constraints of floorplanning using less flexibility first principles. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
36Ron Ho High-performance ULSI: the real limiter to interconnect scaling. Search on Bibsonomy SLIP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF VLSI, wireless, 3D, scaling, proximity, repeaters, wires
36Matthew Moe, Herman Schmit Floorplanning of pipelined array modules using sequence pairs. Search on Bibsonomy ISPD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF pipelined array, floorplan, sequence pair
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