Search results for "wire-sizing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
169	Chung-Ping Chen, D. F. Wong 0001	Optimal Wire-Sizing Function with Fringing Capacitance Consideration.	DAC	1997	DBLP DOI BibTeX RDF
148	Jason Cong, Lei He 0001, Cheng-Kok Koh, David Zhigang Pan	Global interconnect sizing and spacing with consideration of coupling capacitance.	ICCAD	1997	DBLP DOI BibTeX RDF	GISS solutions, asymmetric wire sizing, delay reduction, fringing capacitances, global interconnect sizing and spacing, global wire sizing, interconnect delay minimization, multiple nets, optimal wire sizing, spacing solution, symmetric effective fringing properties, VLSI, coupling capacitance
126	Chung-Ping Chen, Hai Zhou 0001, D. F. Wong 0001	Optimal non-uniform wire-sizing under the Elmore delay model.	ICCAD	1996	DBLP DOI BibTeX RDF	Elmore delay model, IBM RS/6000 workstation, NWSA-db, NWSA-md, NWSA-wd algorithm, general routing trees, maximum sink delay, minimization objectives, optimal nonuniform wire sizing, routing-tree problem, sink-delay bounds, total area, total weighted sink-delays, wire-sizing formula, circuit analysis computing, Lagrangian relaxation
125	Narender Hanchate, Nagarajan Ranganathan	A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Game theory, transmission lines, crosstalk noise, interconnect models, wire sizing, interconnect delay
122	Chris C. N. Chu, Martin D. F. Wong	A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
119	Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay	Interconnect synthesis without wire tapering.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
116	Chris C. N. Chu, D. F. Wong 0001	Greedy wire-sizing is linear time.	ISPD	1998	DBLP DOI BibTeX RDF
106	Chris C. N. Chu, D. F. Wong 0001	A new approach to simultaneous buffer insertion and wire sizing.	ICCAD	1997	DBLP DOI BibTeX RDF	interconnect delay minimization, interconnect area minimization, convex quadratic programming, buffer insertion, wire sizing
105	Takumi Okamoto, Jason Cong	Buffered Steiner tree construction with wire sizing for interconnect layout optimization.	ICCAD	1996	DBLP DOI BibTeX RDF	Steiner Tree, Buffer Insertion, Interconnect Optimization, Wire Sizing
103	Zhuo Li 0001, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia	Fast interconnect synthesis with layer assignment.	ISPD	2008	DBLP DOI BibTeX RDF	buffer insertion, wire sizing, layer assignment, interconnect synthesis
103	Chris C. N. Chu, D. F. Wong 0001	Closed form solutions to simultaneous buffer insertion/sizing and wire sizing.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	buffer insertion, buffer sizing, closed form solution, interconnect optimization, wire sizing
102	Narender Hanchate, Nagarajan Ranganathan	A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise.	VLSI Design	2006	DBLP DOI BibTeX RDF
99	Chris C. N. Chu, D. F. Wong 0001	A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing.	DATE	1998	DBLP DOI BibTeX RDF	Simultaneous buffer and wire sizing, buffer sizing, interconnect optimization, wire sizing
96	Zhuo Li 0001, Nancy Ying Zhou, Weiping Shi	Wire Sizing for Non-Tree Topology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
89	Jason Cong, David Zhigang Pan	Wire width planning for interconnect performance optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
83	Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen	Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
82	Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng 0001	Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
80	Charles J. Alpert, Anirudh Devgan, Stephen T. Quay	Is wire tapering worthwhile?	ICCAD	1999	DBLP DOI BibTeX RDF
79	Jin-Tai Yan, Bo-Yi Chiang, Shi-Qin Huang	Width and Timing-Constrained Wire Sizing for Critical Area Minimization.	APCCAS	2006	DBLP DOI BibTeX RDF
78	Jason Cong, Cheng-Kok Koh	Simultaneous driver and wire sizing for performance and power optimization.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
78	Jason Cong, Cheng-Kok Koh	Simultaneous driver and wire sizing for performance and power optimization.	ICCAD	1994	DBLP DOI BibTeX RDF
78	Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong	Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation.	ISPD	2005	DBLP DOI BibTeX RDF	yield, buffering, design for manufacturing, wire sizing, chemical mechanical polishing (CMP)
78	Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen	Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time.	ISPD	2003	DBLP DOI BibTeX RDF	?-optimal, incremental refinement, pseudo-polynomial, clock tree, wire-sizing, zero-skew
76	Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng 0001	Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
73	Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee	Timing-constrained yield-driven wire sizing for critical area minimization.	ISCAS	2006	DBLP DOI BibTeX RDF
69	Youxin Gao, Martin D. F. Wong	Wire-sizing optimization with inductance consideration using transmission-line model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
67	Min Ni, Seda Ogrenci Memik	Self-heating-aware optimal wire sizing under Elmore delay model.	DATE	2007	DBLP DOI BibTeX RDF
67	Harshit K. Shah, Pun H. Shiu, Brian Bell, Mamie Aldredge, Namarata Sopory, Jeff Davis	Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects.	ICCAD	2002	DBLP DOI BibTeX RDF
67	Song-Ra Pan, Yao-Wen Chang	Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation.	ICCD	2000	DBLP DOI BibTeX RDF
66	Zhaoyun Xing, Prithviraj Banerjee	A parallel algorithm for zero skew clock tree routing.	ISPD	1998	DBLP DOI BibTeX RDF
64	Qing Zhu, Wayne Wei-Ming Dai	High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
63	Jason Cong, Lei He 0001	An efficient approach to simultaneous transistor and interconnect sizing.	ICCAD	1996	DBLP DOI BibTeX RDF	CH-posynomial programs, STIS, driver/buffer, transistor and interconnect sizing, wire sizing problem, circuit CAD, transistor sizing
61	Ke Cao, Jiang Hu, Mosong Cheng	Wire Sizing and Spacing for Lithographic Printability and Timing Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
61	Chris C. N. Chu, Martin D. F. Wong	Greedy wire-sizing is linear time.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
60	Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang	Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning.	ISQED	2002	DBLP DOI BibTeX RDF	Interconnect-Driven Floorplanning, Performance Optimization
60	Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng 0001	Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing.	ICCAD	2003	DBLP DOI BibTeX RDF
59	Minsik Cho, Hua Xiang 0001, Ruchir Puri, David Z. Pan	Track Routing and Optimization for Yield.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
55	Chris C. N. Chu, Martin D. F. Wong	An efficient and optimal algorithm for simultaneous buffer and wire sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
55	Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong	Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
54	Vinita V. Deodhar, Jeffrey A. Davis	Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
54	Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky	Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
53	Magdy A. El-Moursy, Eby G. Friedman	Power characteristics of inductive interconnect.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
51	Rony Kay, Lawrence T. Pileggi	EWA: efficient wiring-sizing algorithm for signal nets and clock nets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
51	Magdy A. El-Moursy, Eby G. Friedman	Optimum wire sizing of RLC interconnect with repeaters.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	power delay product, transient power dissipation, propagation delay, repeater insertion, wire sizing, RLC interconnect
49	Rupak Samanta, Jiang Hu, Peng Li 0001	Discrete buffer and wire sizing for link-based non-tree clock networks.	ISPD	2008	DBLP DOI BibTeX RDF	non-tree, buffer, clock, wire, svm
49	Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong	Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
49	Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown	Clock buffer and wire sizing using sequential programming.	DAC	2006	DBLP DOI BibTeX RDF	skew, robust design, clock tree synthesis
49	Noel Menezes, Ross Baldick, Lawrence T. Pileggi	A sequential quadratic programming approach to concurrent gate and wire sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
49	Noel Menezes, Ross Baldick, Lawrence T. Pileggi	A sequential quadratic programming approach to concurrent gate and wire sizing.	ICCAD	1995	DBLP DOI BibTeX RDF	RC interconnect, optimization, sequential quadratic programming
48	Jason Cong, David Zhigang Pan	Interconnect performance estimation models for design planning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
48	Jason Cong, David Zhigang Pan	Interconnect Delay Estimation Models for Synthesis and Design Planning.	ASP-DAC	1999	DBLP DOI BibTeX RDF
48	Fu-Wei Chen, Yi-Yu Liu	Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture.	DATE	2008	DBLP DOI BibTeX RDF
48	Youxin Gao, D. F. Wong 0001	Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model.	DATE	2000	DBLP DOI BibTeX RDF
45	Minsik Cho, Hua Xiang 0001, Ruchir Puri, David Z. Pan	TROY: Track Router with Yield-driven Wire Planning.	DAC	2007	DBLP DOI BibTeX RDF
43	Noel Menezes, Chung-Ping Chen	Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect.	VLSI Design	1999	DBLP DOI BibTeX RDF
43	Sachin S. Sapatnekar	Wire sizing as a convex optimization problem: exploring the area-delay tradeoff.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
42	Dian Zhou, Ruiming Li	Design and Verification of High-Speed VLSI Physical Design.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	floorplanning and placement, order reduction, parameter extraction, VLSI, delay, interconnect, power, physical design, buffer insertion, power grid, clock distribution, wire sizing
42	Jason Cong, Cheng-Kok Koh	Interconnect layout optimization under higher-order RLC model.	ICCAD	1997	DBLP DOI BibTeX RDF	RATS trees, Steiner routings, bounded-radius Steiner trees, higher-order RLC model, incremental moment computation algorithm, interconnect layout optimization, nonmonotone signal response, required-arrival-time Steiner trees, resistance-inductance-capacitance circuits, routing area, routing cost, routing topologies, shortest-path Steiner trees, signal delay, signal settling time, voltage overshoot, waveform optimization, waveform quality evaluation, wire-sizing optimization, circuit optimisation, topology optimization, delay optimization
42	Xiaopeng Ji, Long Ge, Xiaodong Han, Zhiquan Wang	Wire-Sizing for Interconnect Performance Optimization Considering High Inductance Effects.	ICNSC	2008	DBLP DOI BibTeX RDF
42	Sampath Dechu, Zion Cien Shen, Chris C. N. Chu	An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
42	Sampath Dechu, Zion Cien Shen, Chris C. N. Chu	An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations.	ASP-DAC	2004	DBLP DOI BibTeX RDF
38	Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif	A methodology for the simultaneous design of supply and signal networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
36	Sean X. Shi, David Z. Pan	Wire sizing with scattering effect for nanoscale interconnection.	ASP-DAC	2006	DBLP DOI BibTeX RDF
36	Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi	Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
36	John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin	Optimal wire sizing and buffer insertion for low power and a generalized delay model.	ICCAD	1995	DBLP DOI BibTeX RDF	Timing Optization, Dynamic Power Dissipation, Signal Slew, Dynamic Programming, Elmore Delay
35	Jason Cong, Lei He 0001, Cheng-Kok Koh, David Zhigang Pan	Interconnect sizing and spacing with consideration of couplingcapacitance.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
35	Murat R. Becer, David T. Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj	A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance.	ISQED	2001	DBLP DOI BibTeX RDF
33	Chung-Wei Lin, Lei Rao, Paolo Giusto, Joseph D'Ambrosio, Alberto L. Sangiovanni-Vincentelli	Efficient Wire Routing and Wire Sizing for Weight Minimization of Automotive Systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2015	DBLP DOI BibTeX RDF
33	Chung-Wei Lin, Lei Rao, Paolo Giusto, Joseph D'Ambrosio, Alberto L. Sangiovanni-Vincentelli	An Efficient Wire Routing and Wire Sizing Algorithm for Weight Minimization of Automotive Systems.	DAC	2014	DBLP DOI BibTeX RDF
33	Jiang-An He, Hideaki Kobayashi	Simultaneous Wire Sizing and Wire Spacing in Post-Layout Performance Optimization.	ASP-DAC	1998	DBLP DOI BibTeX RDF
33	Jeremy R. Tolbert, Xin Zhao 0001, Sung Kyu Lim, Saibal Mukhopadhyay	Slew-aware clock tree design for reliable subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	slew, clocks, subthreshold
33	Yu-Yen Mo, Chris C. N. Chu	Hybrid dynamic/quadratic programming algorithm for interconnecttree optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
33	Yu-Min Lee, Charlie Chung-Ping Chen, Yao-Wen Chang, Martin D. F. Wong	Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation.	VLSI Design	2002	DBLP DOI BibTeX RDF
33	Chris C. N. Chu, D. F. Wong 0001	Closed form solution to simultaneous buffer insertion/sizing and wire sizing.	ISPD	1997	DBLP DOI BibTeX RDF
32	Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif	Congestion-driven codesign of power and signal networks.	DAC	2002	DBLP DOI BibTeX RDF	signal routing, wire congestion, codesign, power grid noise
29	I-Jye Lin, Tsui-Yee Ling, Yao-Wen Chang	Statistical circuit optimization considering device andinterconnect process variations.	SLIP	2007	DBLP DOI BibTeX RDF	gate and wire sizing, statistical optimization
29	Mandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex	Impact of interconnect resistance increase on system performance of low power and high performance designs.	SLIP	2006	DBLP DOI BibTeX RDF	interconnect sizing, interconnect technology evaluation, power-delay trade-off, wire sizing
29	Mandeep Bamal, Evelyn Grossar, Michele Stucchi, Karen Maex	Interconnect width selection for deep submicron designs using the table lookup method.	SLIP	2004	DBLP DOI BibTeX RDF	interconnect sizing, power-delay trade-off, wire sizing
29	Chris C. N. Chu, D. F. Wong 0001	VLSI Circuit Performance Optimization by Geometric Programming.	Ann. Oper. Res.	2001	DBLP DOI BibTeX RDF	unary geometric programming, circuit performance optimization, VLSI design, Lagrangian relaxation, gate sizing, transistor sizing, wire sizing
27	Vani Prasad, Madhav P. Desai	Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy.	VLSI Design	2003	DBLP DOI BibTeX RDF
27	Murat R. Becer, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj	Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model .	DATE	2002	DBLP DOI BibTeX RDF
26	Chia-Chun Tsai, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao	X-clock routing based on pattern matching.	SoCC	2008	DBLP DOI BibTeX RDF
26	Kai Wang 0011, Malgorzata Marek-Sadowska	Clock network sizing via sequential linear programming with time-domain analysis.	ISPD	2004	DBLP DOI BibTeX RDF	sequential linear programming, sizing, clock skew, time-domain analysis
22	Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu	Performance-driven Wire Sizing for Analog Integrated Circuits.	ACM Trans. Design Autom. Electr. Syst.	2023	DBLP DOI BibTeX RDF
22	Yoonsang Song, Gangmin Cho, Wonjae Lee, Youngsoo Shin	Simultaneous Clock Wire Sizing and Shield Insertion for Minimizing Routing Blockage.	MLCAD	2023	DBLP DOI BibTeX RDF
22	Meng Liu, Zhiwei Zhang, Wenqin Sun, Donglin Wang	Optimization of clock mesh based on wire sizing variation.	ISOCC	2017	DBLP DOI BibTeX RDF
22	Chris Chu	Wire Sizing.	Encyclopedia of Algorithms	2016	DBLP DOI BibTeX RDF
22	Shikha Singh 0004, V. Sulochana Verma	Reduction of Crosstalk Noise and Delay in VLSI Interconnects Using Schmitt Trigger as a Buffer and Wire Sizing.	ACITY (3)	2012	DBLP DOI BibTeX RDF
22	Rupak Samanta, Jiang Hu, Peng Li 0001	Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
22	Zhi-Wei Chen, Jin-Tai Yan	Width-constrained wire sizing for non-tree interconnections.	ISCAS	2010	DBLP DOI BibTeX RDF
22	Sanghamitra Roy, Charlie Chung-Ping Chen	Wire Sizing.	Handbook of Algorithms for Physical Design Automation	2008	DBLP DOI BibTeX RDF
22	Chris Chu	Wire Sizing.	Encyclopedia of Algorithms	2008	DBLP DOI BibTeX RDF
22	Vinita V. Deodhar, Jeffrey A. Davis	Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects.	IEEE Trans. Circuits Syst. I Regul. Pap.	2008	DBLP DOI BibTeX RDF
22	Narender Hanchate, Nagarajan Ranganathan	Integrated Gate and Wire Sizing at Post Layout Level.	ISVLSI	2007	DBLP DOI BibTeX RDF
22	Jin-Tai Yan, Shi-Qin Huang, Zhi-Wei Chen	Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance.	ICECS	2007	DBLP DOI BibTeX RDF
22	Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny	Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Magdy A. El-Moursy, Eby G. Friedman	Optimum wire sizing of RLC interconnect with repeaters .	Integr.	2004	DBLP DOI BibTeX RDF
22	Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan	Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery.	PATMOS	2004	DBLP DOI BibTeX RDF
22	Shlomo Greenberg, Ido Bloch, Moti Horwitz, Avishay Maman	Optimization of chip level clock tree performance by using simultaneous drivers and wire sizing.	ICECS	2004	DBLP DOI BibTeX RDF
22	Ting-Yuan Wang, Charlie Chung-Ping Chen	Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm.	ISQED	2002	DBLP DOI BibTeX RDF