Search results for "ISLPD"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	S. Turgis, Nadine Azémard, Daniel Auvergne	Explicit evaluation of short circuit power dissipation for CMOS logic structures.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Sven Wuytack, Francky Catthoor, Hugo De Man	Transforming set data types to power optimal data structures.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Premal Buch, Shen Lin 0001, Vijay Nagasamy, Ernest S. Kuh	Techniques for fast circuit simulation applied to power estimation of CMOS circuits.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Rafael Fried, Reuven Holzer	Low power and EMI, high frequency, crystal oscillator.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin	Unifying carry-sum and signed-digital number representations for low power.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Kei-Yong Khoo, Alan N. Willson Jr.	Charge recovery on a databus.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Kimiyoshi Usami, Mark Horowitz	Clustered voltage scaling technique for low-power design.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Vivek Tiwari, Sharad Malik, Pranav Ashar	Guarded evaluation: pushing power management to logic synthesis/design.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Alan Kramer, Roberto Canegallo, Mauro Chinosi, D. Doise, Giovanni Gozzini, Pier Luigi Rolandi, Marco Sabatini, P. Zabberoni	Ultra-low-power analog associative memory core using flash-EEPROM-based programmable capacitors.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Paul E. Landman, Jan M. Rabaey	Activity-sensitive architectural power analysis for the control path.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Massoud Pedram, Robert W. Brodersen, Kurt Keutzer (eds.)	Proceedings of the 1995 International Symposium on Low Power Design 1995, Dana Point, California, USA, April 23-26, 1995	ISLPD	1995	DBLP BibTeX RDF
1	Michele Favalli, Luca Benini	Analysis of glitch power dissipation in CMOS ICs.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Anthony Correale Jr.	Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers.	ISLPD	1995	DBLP DOI BibTeX RDF	PowerPC
1	M. Tachibana, S. Kurosawa, R. Nojima, Norman Kojima, Masaaki Yamada, Takashi Mitsuhashi, Nobuyuki Goto	Power and area optimization by reorganizing CMOS complex gate circuits.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Alan Kramer, John S. Denker, B. Flower, J. Moroney	2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Aurobindo Dasgupta, Ramesh Karri	Simultaneous scheduling and binding for power minimization during microarchitecture synthesis.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Anthony M. Hill, Sung-Mo Kang	Determining accuracy bounds for simulation-based switching activity estimation.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Manjit Borah, Robert Michael Owens, Mary Jane Irwin	Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Walter Davis	The CAD challenges of designing low power, high performance VLSI system.	ISLPD	1995	DBLP DOI BibTeX RDF
1	David J. Frank, Paul M. Solomon	Electroid-oriented adiabatic switching circuits.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Ching-Long Su, Alvin M. Despain	Cache design trade-offs for power and performance optimization: a case study.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Manjit Borah, Robert Michael Owens, Mary Jane Irwin	High-throughput and low-power DSP using clocked-CMOS circuitry.	ISLPD	1995	DBLP DOI BibTeX RDF
1	William A. Chren Jr.	Low delay-power product CMOS design using one-hot residue coding.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Luca Benini, Giovanni De Micheli	Transformation and synthesis of FSMs for low-power gated-clock implementation.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Diana Marculescu, Radu Marculescu, Massoud Pedram	Information theoretic measures of energy consumption at register transfer level.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Enric Musoll, Jordi Cortadella	High-level synthesis techniques for reducing the activity of functional units.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Uming Ko, Poras T. Balsara, Ashwini K. Nanda	Energy optimization of multi-level processor cache architectures.	ISLPD	1995	DBLP DOI BibTeX RDF
1	José Monteiro 0001, Srinivas Devadas	Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Christian Piguet, Jean-Marc Masgonty, Vincent von Kaenel, Thierry Schneider	Logic design for low-voltage/low-power CMOS circuits.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Christos A. Papachristou, Mark Spining, Mehrdad Nourani	A multiple clocking scheme for low power RTL design.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Charlie X. Huang, Bill Zhang, An-Chang Deng, Burkhard Swirski	The design and implementation of PowerMill.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Vamshi Veeramachaneni, Akhilesh Tyagi, Suresh Rajgopal	Re-encoding for low power state assignment of FSMs.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Salil Raje, Majid Sarrafzadeh	Variable voltage scheduling.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Peter Feldmann, Gary D. Hachtel, Fabio Somenzi	CMOS dynamic power estimation based on collapsible current source transistor modeling.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Farid N. Najm	Towards a high-level power estimation capability.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Phillip E. Allen, Benjamin J. Blalock, Gabriel A. Rincon	Low voltage analog circuits using standard CMOS technology.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Peter A. Beerel, Cheng-Ta Hsieh, Suhrid A. Wadekar	Estimation of energy consumption in speed-independent control circuits.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Ramesh Panwar, David A. Rennels	Reducing the frequency of tag compares for low power I-cache design.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Christopher K. Lennard, A. Richard Newton	An estimation technique to guide low power resynthesis algorithms.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Alexey Glebov, David T. Blaauw, Larry G. Jones	Transistor reordering for low power CMOS gates using an SP-BDD representation.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Jae W. Chung, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin	Optimization of power dissipation and skew sensitivity in clock buffer synthesis.	ISLPD	1995	DBLP DOI BibTeX RDF

Publications at "ISLPD"( http://dblp.L3S.de/Venues/ISLPD )