Search results for "FPT"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Georgios Tzimpragos, Da Cheng, Stephanie Tapp, Balakrishna Jayadev, Amitava Majumdar 0002	Application debug in FPGAs in the presence of multiple asynchronous clocks.	FPT	2016	DBLP DOI BibTeX RDF
1	Andrew Putnam	The configurable cloud - accelerating hyperscale datacenter services with FPGAs.	FPT	2016	DBLP DOI BibTeX RDF
1	Tze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono	A modular architecture for dynamically reconfigurable middlebox with customized reconfiguration handler.	FPT	2016	DBLP DOI BibTeX RDF
1	Muhammed Al Kadi, Michael Hübner 0001	Integer computations with soft GPGPU on FPGAs.	FPT	2016	DBLP DOI BibTeX RDF
1	Ayesha Khalid, James Howe, Ciara Rafferty, Máire O'Neill	Time-independent discrete Gaussian sampling for post-quantum cryptography.	FPT	2016	DBLP DOI BibTeX RDF
1	Taito Manabe, Yuichiro Shibata, Kiyoshi Oguri	FPGA implementation of a real-time super-resolution system using a convolutional neural network.	FPT	2016	DBLP DOI BibTeX RDF
1	Zhenxue He, Limin Xiao, Longbing Zhang, Fei Gu 0001, Zhisheng Huo, Mingfa Zhu, Li Ruan, Rui Liu, Xiang Wang 0006	EMA-FPRMs: An efficient minimization algorithm for fixed polarity Reed-Muller expressions.	FPT	2016	DBLP DOI BibTeX RDF
1	Song Xu, Qiang Liu 0011, Tao Li, Hongxiang Fan	IC security evaluation against fault injection attack based on FPGA emulation.	FPT	2016	DBLP DOI BibTeX RDF
1	He Qi, Oluseyi A. Ayorinde, Benton H. Calhoun	An energy-efficient near/sub-threshold FPGA interconnect architecture using dynamic voltage scaling and power-gating.	FPT	2016	DBLP DOI BibTeX RDF
1	Junying Chen, Shunfeng Zhou, Huaqing Min	Implementation of parallel medical ultrasound imaging algorithm on CAPI-enabled FPGA.	FPT	2016	DBLP DOI BibTeX RDF
1	Tianqi Liu, Naveen Kumar Dumpala, Russell Tessier	Hybrid hard NoCs for efficient FPGA communication.	FPT	2016	DBLP DOI BibTeX RDF
1	Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotásek	Functional verification as a tool for monitoring impact of faults in SRAM-based FPGAs.	FPT	2016	DBLP DOI BibTeX RDF
1	Jakub Lojda, Jakub Podivinsky, Martin Krcma, Zdenek Kotásek	HLS-based fault tolerance approach for SRAM-based FPGAs.	FPT	2016	DBLP DOI BibTeX RDF
1	Donald G. Bailey	Identification of Trax threats using pattern matching.	FPT	2016	DBLP DOI BibTeX RDF
1	Nguyen T. H. Nguyen, Dimitris Agiakatsikas, Ediz Çetin, Oliver Diessel	Dynamic scheduling of voter checks in FPGA-based TMR systems.	FPT	2016	DBLP DOI BibTeX RDF
1	Naifeng Jing, Taozhong Li, Zhongyuan Zhao 0004, Wei Jin 0004, Yanan Sun 0003, Weifeng He, Zhigang Mao	Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory.	FPT	2016	DBLP DOI BibTeX RDF
1	Sumedh Guha, Wen Wang 0007, Shafeeq Ibraheem, Mahesh Balakrishnan 0001, Jakub Szefer	Design and implementation of open-source SATA III core for Stratix V FPGAs.	FPT	2016	DBLP DOI BibTeX RDF
1	Tianqi Wang, Linlin Zheng, Xi Jin 0002, Bo Peng, Chuanjun Wang	FPGA acceleration of TreePM N-body simulations for Modified Newton Dynamics.	FPT	2016	DBLP DOI BibTeX RDF
1	Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura	A memory-based realization of a binarized deep convolutional neural network.	FPT	2016	DBLP DOI BibTeX RDF
1	Kumar H. B. Chethan, Shubham Agarwal, Nachiket Kapre	Deflection routing for multi-level FPGA overlay NoCs.	FPT	2016	DBLP DOI BibTeX RDF
1	Mengjun Li, Yongxin Zhu 0001, Xu Wang 0010, Tian Huang, Weida Chen, Bin Liu, Yishu Mao	Evaluation of variable precision computing with variable precision FFT implementation on FPGA.	FPT	2016	DBLP DOI BibTeX RDF
1	Zhiqiang Liu, Yong Dou, Jingfei Jiang, Jinwei Xu	Automatic code generation of convolutional neural networks in FPGA implementation.	FPT	2016	DBLP DOI BibTeX RDF
1	Sean Fox, Stephen Tridgell, Craig T. Jin, Philip Heng Wai Leong	Random projections for scaling machine learning on FPGAs.	FPT	2016	DBLP DOI BibTeX RDF
1	Grace Zgheib, Paolo Ienne	Automatic wire modeling to explore novel FPGA architectures.	FPT	2016	DBLP DOI BibTeX RDF
1	Qi Zhan, Min Gao, Li Jiao, Wei Cao 0002, Xuegong Zhou, Lingli Wang	High performance Deformable Part Model accelerator based on FPGA.	FPT	2016	DBLP DOI BibTeX RDF
1	Wei Ting Loke, Chin Yang Koay	Energy-aware scheduling for task adaptive FPGAs.	FPT	2016	DBLP DOI BibTeX RDF
1	Jason Helge Anderson	High-level synthesis - the right side of history.	FPT	2016	DBLP DOI BibTeX RDF
1	Nandeesha Veeranna, Benjamin Carrión Schäfer	Hardware Trojan avoidance and detection for dynamically re-configurable FPGAs.	FPT	2016	DBLP DOI BibTeX RDF
1	Vincent Migliore, Maria Mendez Real, Vianney Lapotre, Arnaud Tisserand, Caroline Fontaine, Guy Gogniat	Fast polynomial arithmetic for Somewhat Homomorphic Encryption operations in hardware with Karatsuba algorithm.	FPT	2016	DBLP DOI BibTeX RDF
1	Kosuke Tatsumura, Sadegh Yazdanshenas, Vaughn Betz	High density, low energy, magnetic tunnel junction based block RAMs for memory-rich FPGAs.	FPT	2016	DBLP DOI BibTeX RDF
1	Jorge Echavarria, Stefan Wildermann, Andreas Becher, Jürgen Teich, Daniel Ziener	FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs.	FPT	2016	DBLP DOI BibTeX RDF
1	Shengjia Shao, Oskar Mencer, Wayne Luk	Dataflow design for optimal incremental SVM training.	FPT	2016	DBLP DOI BibTeX RDF
1	Xinyu Chen, Yong Gu, Chenxu Wang, Xuguang Guan	Asymmetric multiprocessing for motion control based on Zynq SoC.	FPT	2016	DBLP DOI BibTeX RDF
1	Björn Liebig, Andreas Koch 0001	High-level synthesis of resource-shared microarchitectures from irregular complex C-code.	FPT	2016	DBLP DOI BibTeX RDF
1	Juan Escobedo, Mingjie Lin	Tessellation-based multi-block memory mapping scheme for high-level synthesis with FPGA.	FPT	2016	DBLP DOI BibTeX RDF
1	Yuto Arai, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi	An efficient FPGA implementation of Mahalanobis distance-based outlier detection for streaming data.	FPT	2016	DBLP DOI BibTeX RDF
1	Lester Kalms, Ahmed Elhossini, Ben H. H. Juurlink	FPGA based hardware accelerator for KAZE feature extraction algorithm.	FPT	2016	DBLP DOI BibTeX RDF
1	Jose P. Pinilla, Steven J. E. Wilton	Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designs.	FPT	2016	DBLP DOI BibTeX RDF
1	Hiroshi Nakahara, Tetsui Ohkubo, Hideki Shimura, Ryotaro Sakai, Chiharu Tsuruta, Takahiro Kaneda, Hideharu Amano	Trax solver on Zynq using incremental update algorithm.	FPT	2016	DBLP DOI BibTeX RDF
1	Akira Kojima	Trax player implementation on FPGA using high level synthesis tool.	FPT	2016	DBLP DOI BibTeX RDF
1	Denis Matousek, Jan Korenek, Viktor Pus	High-speed regular expression matching with pipelined automata.	FPT	2016	DBLP DOI BibTeX RDF
1	Roberto DiCecco, Griffin Lacey, Jasmina Vasiljevic, Paul Chow, Graham W. Taylor, Shawki Areibi	Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks.	FPT	2016	DBLP DOI BibTeX RDF
1	Jagath Weerasinghe, Raphael Polig, François Abel, Christoph Hagleitner	Network-attached FPGAs for data center applications.	FPT	2016	DBLP DOI BibTeX RDF
1	Naoki Ando, Koichiro Masuyama, Hayate Okuhara, Hideharu Amano	Variable pipeline structure for Coarse Grained Reconfigurable Array CMA.	FPT	2016	DBLP DOI BibTeX RDF
1	Dennis R. E. Gnad, Fabian Oboril, Saman Kiamehr, Mehdi Baradaran Tahoori	Analysis of transient voltage fluctuations in FPGAs.	FPT	2016	DBLP DOI BibTeX RDF
1	Tian Xia 0007, Jean-Christophe Prévotet, Fabienne Nouvel	Hypervisor mechanisms to manage FPGA reconfigurable accelerators.	FPT	2016	DBLP DOI BibTeX RDF
1	Haomiao Wang, Ming Zhang, Thiagaraj Prabu, Oliver Sinnen	FPGA-based acceleration of FDAS module using OpenCL.	FPT	2016	DBLP DOI BibTeX RDF
1	Deshya Wijesundera, Alok Prakash, Thambipillai Srikanthan	Rapid design space exploration for soft core processor customization and selection.	FPT	2016	DBLP DOI BibTeX RDF
1	Maolin Wang, Ho-Cheung Ng, Bob M. F. Chung, B. Sharat Chandra Varma 0001, Manish Kumar Jaiswal, Kevin K. Tsia, Ho Cheung Shum, Hayden Kwok-Hay So	Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA.	FPT	2016	DBLP DOI BibTeX RDF
1	Zhuoran Zhao, Dimitris Agiakatsikas, Nguyen T. H. Nguyen, Ediz Çetin, Oliver Diessel	Fine-grained module-based error recovery in FPGA-based TMR systems.	FPT	2016	DBLP DOI BibTeX RDF
1	Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek	Random stimuli generation based on a stochastic context-free grammar.	FPT	2016	DBLP DOI BibTeX RDF
1	Hiroki Nakahara, Akira Jinguji, Tomonori Fujii, Simpei Sato	An acceleration of a random forest classification using Altera SDK for OpenCL.	FPT	2016	DBLP DOI BibTeX RDF
1	Yuchen Song, Shaojun Wang, Brent Nelson, Junbao Li, Yu Peng (eds.)	2016 International Conference on Field-Programmable Technology, FPT 2016, Xi'an, China, December 7-9, 2016	FPT	2016	DBLP BibTeX RDF
1	David Sidler, Ken Eguro	Debugging framework for FPGA-based soft processors.	FPT	2016	DBLP DOI BibTeX RDF
1	Qian Zhao 0001, Takuya Nakamichi, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi	hCODE: An open-source platform for FPGA accelerators.	FPT	2016	DBLP DOI BibTeX RDF
1	Vincent Mirian, Paul Chow	Exploring pipe implementations using an OpenCL framework for FPGAs.	FPT	2015	DBLP DOI BibTeX RDF
1	Joshua S. Monson, Brad L. Hutchings	Using source-to-source compilation to instrument circuits for debug with High Level Synthesis.	FPT	2015	DBLP DOI BibTeX RDF
1	Andrew Bitar, Mohamed S. Abdelfattah, Vaughn Betz	Bringing programmability to the data plane: Packet processing with a NoC-enhanced FPGA.	FPT	2015	DBLP DOI BibTeX RDF
1	James Arram, Moritz Pflanzer, Thomas Kaplan, Wayne Luk	FPGA acceleration of reference-based compression for genomic data.	FPT	2015	DBLP DOI BibTeX RDF
1	Liwei Yang, Magzhan Ikram, Swathi T. Gurumani, Suhaib A. Fahmy, Deming Chen, Kyle Rupnow	JIT trace-based verification for high-level synthesis.	FPT	2015	DBLP DOI BibTeX RDF
1	Jeffrey Goeders, Steven J. E. Wilton	Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAs.	FPT	2015	DBLP DOI BibTeX RDF
1	Qing Lu, Chiu-Wing Sham, Francis C. M. Lau 0002	An architecture-algorithm co-design of artificial intelligence for Trax player.	FPT	2015	DBLP DOI BibTeX RDF
1	Sebastian Meisner, Marco Platzner	Comparison of thread signatures for error detection in hybrid multi-cores.	FPT	2015	DBLP DOI BibTeX RDF
1	Mengyuan Gu, Kaiyuan Guo, Wenqiang Wang, Yu Wang 0002, Huazhong Yang	An FPGA-based real-time simultaneous localization and mapping system.	FPT	2015	DBLP DOI BibTeX RDF
1	Bony H. K. Chen, Paul Y. S. Cheung, Peter Y. K. Cheung, Yu-Kwong Kwok	An efficient architecture for zero overhead data en-/decryption using reconfigurable cryptographic engine.	FPT	2015	DBLP DOI BibTeX RDF
1	Cheng Liu, Ho-Cheung Ng, Hayden Kwok-Hay So	QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay.	FPT	2015	DBLP DOI BibTeX RDF
1	Hyunseok Park, Shreel Vijayvargiya, André DeHon	Energy minimization in the time-space continuum.	FPT	2015	DBLP DOI BibTeX RDF
1	Alex Rodionov, Jonathan Rose	Automatic FPGA system and interconnect construction with multicast and customizable topology.	FPT	2015	DBLP DOI BibTeX RDF
1	Andreas Becher, Daniel Ziener, Klaus Meyer-Wegener, Jürgen Teich	A co-design approach for accelerated SQL query processing via FPGA-based data filtering.	FPT	2015	DBLP DOI BibTeX RDF
1	Fatemeh Eslami, Steven J. E. Wilton	An adaptive virtual overlay for fast trigger insertion for FPGA debug.	FPT	2015	DBLP DOI BibTeX RDF
1	Yubin Li, Yuliang Sun, Guohao Dai, Yuzhi Wang, Jiacai Ni, Yu Wang 0002, Guoliang Li 0001, Huazhong Yang	A self-aware data compression system on FPGA in Hadoop.	FPT	2015	DBLP DOI BibTeX RDF
1	Akira Kojima	An Implementation of Trax player using programmable SoC.	FPT	2015	DBLP DOI BibTeX RDF
1	Jianfeng Zhang, Paul Chow, Hengzhu Liu	FPGA implementation of low-power and high-PSNR DCT/IDCT architecture based on adaptive recoding CORDIC.	FPT	2015	DBLP DOI BibTeX RDF
1	Shuanglong Liu, Grigorios Mingas, Christos-Savvas Bouganis	An exact MCMC accelerator under custom precision regimes.	FPT	2015	DBLP DOI BibTeX RDF
1	Stephen Tridgell, Duncan J. M. Moss, Nicholas J. Fraser, Philip Heng Wai Leong	Braiding: A scheme for resolving hazards in kernel adaptive filters.	FPT	2015	DBLP DOI BibTeX RDF
1	Liwei Yang, Swathi T. Gurumani, Deming Chen, Kyle Rupnow	Behavioral-level IP integration in high-level synthesis.	FPT	2015	DBLP DOI BibTeX RDF
1	Jongsok Choi, Stephen Dean Brown, Jason Helge Anderson	Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware.	FPT	2015	DBLP DOI BibTeX RDF
1	Takumi Fujimori, Tomoya Akabe, Yoshizumi Ito, Kouta Akagi, Shinya Furukawa, Hiroki Shinba, Aoi Tanibata, Minoru Watanabe	FPGA Trax Solver based on a neural network design.	FPT	2015	DBLP DOI BibTeX RDF
1	Ana Petkovska, Grace Zgheib, David Novo, Muhsen Owaida, Alan Mishchenko, Paolo Ienne	Improved carry chain mapping for the VTR flow.	FPT	2015	DBLP DOI BibTeX RDF
1	Yuki Murakami	FPGA implementation of a SIMD-based array processor with torus interconnect.	FPT	2015	DBLP DOI BibTeX RDF
1	Kubilay Atasu	Leftmost longest regular expression matching in reconfigurable logic.	FPT	2015	DBLP DOI BibTeX RDF
1	Jifang Jin, Jian Yan 0002, Xuegong Zhou, Lingli Wang	An adaptive cross-layer fault recovery solution for reconfigurable SoCs.	FPT	2015	DBLP DOI BibTeX RDF
1	Elias Vansteenkiste, Alireza Kaviani, Henri Fraisse	Analyzing the divide between FPGA academic and commercial results.	FPT	2015	DBLP DOI BibTeX RDF
1	Donald G. Bailey, Sharmil Randhawa, Jim S. Jimmy Li	Advanced Bayer demosaicing on FPGAs.	FPT	2015	DBLP DOI BibTeX RDF
1	Haomiao Wang, Oliver Sinnen	FPGA based acceleration of FDAS module for Pulsar Search.	FPT	2015	DBLP DOI BibTeX RDF
1	Jens Huthmann, Andreas Koch 0001	Optimized high-level synthesis of SMT multi-threaded hardware accelerators.	FPT	2015	DBLP DOI BibTeX RDF
1	James Stanley Targett, Xinyu Niu, Francis P. Russell, Wayne Luk, Stephen Jeffress, Peter D. Düben	Lower precision for higher accuracy: Precision and resolution exploration for shallow water equations.	FPT	2015	DBLP DOI BibTeX RDF
1	Jasmina Vasiljevic, Ralph Wittig, Paul Schumacher, Jeff Fifield, Fernando Martinez-Vallina, Henry Styles, Paul Chow	OpenCL library of stream memory components targeting FPGAs.	FPT	2015	DBLP DOI BibTeX RDF
1	Felix Winterstein, Kermin Fleming, Hsin-Jung Yang, John Wickerson, George A. Constantinides	Custom-sized caches in application-specific memory hierarchies.	FPT	2015	DBLP DOI BibTeX RDF
1	Bajaj Ronak, Suhaib A. Fahmy	Minimizing DSP block usage through multi-pumping.	FPT	2015	DBLP DOI BibTeX RDF
1	Junyi Xie, Xinyu Niu, Andy K. S. Lau, Kevin K. Tsia, Hayden Kwok-Hay So	Accelerated cell imaging and classification on FPGAs for quantitative-phase asymmetric-detection time-stretch optical microscopy.	FPT	2015	DBLP DOI BibTeX RDF
1		2015 International Conference on Field Programmable Technology, FPT 2015, Queenstown, New Zealand, December 7-9, 2015	FPT	2015	DBLP BibTeX RDF
1	Jason Motha, Andrew Bainbridge-Smith, Steve Weddell	Cryptographic techniques in redundant number systems.	FPT	2015	DBLP DOI BibTeX RDF
1	Donald G. Bailey	Smart camera for Trax playing robot.	FPT	2015	DBLP DOI BibTeX RDF
1	Naru Sugimoto, Takuji Mitsuishi, Takahiro Kaneda, Chiharu Tsuruta, Ryotaro Sakai, Hideki Shimura, Hideharu Amano	Trax solver on Zynq with Deep Q-Network.	FPT	2015	DBLP DOI BibTeX RDF
1	Faisal Mahmood, Mart Toots, Lars-Goran Ofverstedt, Ulf Skoglund	2D Discrete Fourier Transform with simultaneous edge artifact removal for real-time applications.	FPT	2015	DBLP DOI BibTeX RDF
1	Ian Graves, Adam M. Procter, William L. Harrison, Gerard Allwein	Provably Correct Development of reconfigurable hardware designs via equational reasoning.	FPT	2015	DBLP DOI BibTeX RDF
1	Ryo Okuda, Tomohiro Tanaka, Keisuke Yamamoto, Takumu Yahagi, Kazuya Tanigawa	Development of a Trax Artificial Intelligence algorithm using path and edge.	FPT	2015	DBLP DOI BibTeX RDF
1	Kevin E. Murray, Vaughn Betz	HETRIS: Adaptive floorplanning for heterogeneous FPGAs.	FPT	2015	DBLP DOI BibTeX RDF
1	Size Xiao, Adam Postula, Neil W. Bergmann	Hardware design of a fast, parallel Random Tree path planner.	FPT	2015	DBLP DOI BibTeX RDF

Publications at "FPT"( http://dblp.L3S.de/Venues/FPT )